Setting up a 64-bit FPGA build environment for the USRP-E3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)

Environment successfully initialized.
make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1 EXTRA_DEFS="RFNOC=1 E310=1"
make[1]: Entering directory '/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
BUILDER: Checking tools...
* GNU bash, version 4.4.20(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.9
* Vivado v2017.4 (64-bit)

Using parser configuration from: /home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/dev_config.json
[00:00:00] Executing command: vivado -mode batch -source /home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build_e300.tcl -log build.log -journal e300.jou
[00:00:00] Current task: Initialization +++ Current Phase: Starting

CRITICAL WARNING: [Common 17-741] No write access right to the local Tcl store at '/home/jon/.Xilinx/Vivado/2017.4/XilinxTclStore'. XilinxTclStore is reverted to the installation area. If you want to use local Tcl Store, please change the access right and relaunch Vivado.
[00:00:19] Current task: Initialization +++ Current Phase: Finished

[00:00:19] Executing Tcl: synth_design -top e300 -part xc7z020clg484-3 -verilog_define RFNOC=1 -verilog_define E310=1 -verilog_define GIT_HASH=32'hfbb85bdf -directive AreaOptimized_high
[00:00:19] Starting Synthesis Command
[00:00:19] Current task: Synthesis +++ Current Phase: Starting

CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks clk_fpga_0]'. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:20]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks clk0]'. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks clkdv]'. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28]
[00:01:52] Current task: Synthesis +++ Current Phase: Loading Part and Timing Information

[00:02:12] Current task: Synthesis +++ Current Phase: RTL Component Statistics

[00:02:12] Current task: Synthesis +++ Current Phase: RTL Hierarchical Component Statistics

[00:02:12] Current task: Synthesis +++ Current Phase: Part Resource Summary

[00:03:15] Current task: Synthesis +++ Current Phase: Cross Boundary and Area Optimization

[00:06:01] Current task: Synthesis +++ Current Phase: Applying XDC Timing Constraints

[00:06:05] Current task: Synthesis +++ Current Phase: Timing Optimization

[00:06:31] Current task: Synthesis +++ Current Phase: Technology Mapping

[00:07:43] Current task: Synthesis +++ Current Phase: IO Insertion

[00:07:43] Current task: Synthesis +++ Current Phase: Flattening Before IO Insertion

[00:07:48] Current task: Synthesis +++ Current Phase: Final Netlist Cleanup

[00:08:01] Current task: Synthesis +++ Current Phase: Renaming Generated Instances

[00:08:13] Current task: Synthesis +++ Current Phase: Rebuilding User Hierarchy

[00:08:22] Current task: Synthesis +++ Current Phase: Renaming Generated Ports

[00:08:26] Current task: Synthesis +++ Current Phase: Handling Custom Attributes

[00:08:26] Current task: Synthesis +++ Current Phase: Renaming Generated Nets

[00:08:26] Current task: Synthesis +++ Current Phase: Writing Synthesis Report

[00:08:30] Current task: Synthesis +++ Current Phase: Finished

[00:08:30] Translating Synthesized Netlist
[00:08:30] Current task: Translating Synthesized Netlist +++ Current Phase: Starting
CRITICAL WARNING: [Designutils 20-1281] Could not find module 'mig_7series_0'. The XDC file /home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc will not be read for this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_hb31/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb47'. The XDC file /home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_hb47/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks clk0]'. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28]
CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks clkdv]'. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28]
CRITICAL WARNING: [Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:28]
CRITICAL WARNING: [Common 17-161] Invalid option value '#' specified for 'objects'. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:53]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
[00:10:00] Current task: Translating Synthesized Netlist +++ Current Phase: Starting

[00:11:51] Current task: Translating Synthesized Netlist +++ Current Phase: Finished

[00:11:51] Executing Tcl: report_drc -ruledeck methodology_checks -file /home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC_sg3/methodology.rpt
[00:11:51] Starting DRC Command
[00:11:51] Current task: DRC +++ Current Phase: Starting

CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
[00:14:23] Current task: DRC +++ Current Phase: Finished

[00:14:23] Executing Tcl: opt_design -directive NoBramPowerOpt
[00:14:23] Starting Logic Optimization Command
[00:14:23] Current task: Logic Optimization +++ Current Phase: Starting

[00:14:24] Current task: Logic Optimization +++ Current Phase: Finished

[00:14:24] Starting DRC Task
[00:14:24] Current task: DRC +++ Current Phase: Starting

[00:14:26] Current task: DRC +++ Current Phase: Finished

[00:14:26] Starting Logic Optimization Task
[00:14:26] Current task: Logic Optimization +++ Current Phase: Starting

CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
[00:14:52] Current task: Logic Optimization +++ Current Phase: 1 Retarget

[00:15:06] Current task: Logic Optimization +++ Current Phase: 2 Constant propagation

[00:15:11] Current task: Logic Optimization +++ Current Phase: 3 Sweep

[00:15:30] Current task: Logic Optimization +++ Current Phase: 4 BUFG optimization

[00:15:36] Current task: Logic Optimization +++ Current Phase: 5 Shift Register Optimization

[00:15:46] Current task: Logic Optimization +++ Current Phase: Finished

[00:15:46] Starting Connectivity Check Task
[00:15:46] Current task: Connectivity Check +++ Current Phase: Starting

[00:15:51] Current task: Connectivity Check +++ Current Phase: Finished

[00:15:51] Executing Tcl: place_design -directive ExtraNetDelay_high
[00:15:51] Starting Placer Command
[00:15:51] Current task: Placer +++ Current Phase: Starting

[00:16:08] Starting Placer Task
[00:16:08] Current task: Placer +++ Current Phase: Starting

[00:16:08] Current task: Placer +++ Current Phase: 1 Placer Initialization

[00:16:08] Current task: Placer +++ Current Phase: 1.1 Placer Initialization Netlist Sorting

CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
[00:16:36] Current task: Placer +++ Current Phase: 1.2 IO Placement/ Clock Placement/ Build Placer Device

CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
[00:17:12] Current task: Placer +++ Current Phase: 1.3 Build Placer Netlist Model

CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I0' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/I1' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
CRITICAL WARNING: [Constraints 18-514] set_max_delay: Path segmentation by forcing 'CAT_SCLK_MUX/S' to be timing endpoint. There will be no hold timing paths to this pin unless set_min_delay is used to constrain the paths. [/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300/e310_timing.xdc:58]
[00:18:05] Current task: Placer +++ Current Phase: 1.4 Constrain Clocks/Macros

[00:18:06] Current task: Placer +++ Current Phase: 2 Global Placement

[00:19:25] Current task: Placer +++ Current Phase: 3 Detail Placement

[00:19:25] Current task: Placer +++ Current Phase: 3.1 Commit Multi Column Macros
[00:20:00] Current task: Placer +++ Current Phase: 3.1 Commit Multi Column Macros

[00:20:15] Current task: Placer +++ Current Phase: 3.3 Area Swap Optimization

[00:20:16] Current task: Placer +++ Current Phase: 3.4 Pipeline Register Optimization

[00:20:16] Current task: Placer +++ Current Phase: 3.5 Small Shape Detail Placement

ERROR: [Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 13300 slices in the pblock, of which 8802 slices are available, however, the unplaced instances require 9260 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced.
ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed please check previous errors for details.'
ERROR: [Common 17-69] Command failed: Placer could not place all instances
[00:20:49] Current task: Placer +++ Current Phase: Finished
[00:20:49] Process terminated. Status: Failure

========================================================
Warnings:           655
Critical Warnings:  32
Errors:             3

Makefile.e300.inc:98: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory '/home/jon/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
Makefile:70: recipe for target 'E310_RFNOC_sg3' failed
make: *** [E310_RFNOC_sg3] Error 2
--Using the following blocks to generate image:
    * fft
    * window
    * fosphor
Adding CE instantiation file for 'E310_RFNOC_sg3'
changing temporarily working directory to /home/jon/rfnoc/src/uhd/fpga-src/usrp3/tools/scripts/../../top/e300