palindrome@palindrome1001:~/workarea-rfnoc/uhd/fpga-src/usrp3/tools/scripts$ ./uhd_image_builder.py window fft -d x310 -t X310_RFNOC_HG -m 5 --fill-with-fifos --Using the following blocks to generate image: * window * fft Adding CE instantiation file for 'X310_RFNOC_HG' changing temporarily working directory to /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/tools/scripts/../../top/x300 Setting up a 64-bit FPGA build environment for the USRP-X3x0... - Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin) Environment successfully initialized. make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 TOP_MODULE=x300 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 " make[1]: Entering directory '/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300' BUILDER: Checking tools... * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) * Python 2.7.12 * Vivado v2017.4_AR70455 (64-bit) Using parser configuration from: /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/dev_config.json [00:00:00] Executing command: vivado -mode batch -source /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build_x300.tcl -log build.log -journal x300.jou CRITICAL WARNING: [filemgmt 20-1440] File '/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v' already exists in the project as a part of sub-design file '/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'. Explicitly adding the file outside the scope of the sub-design can lead to unintended behaviors and is not recommended. [00:00:12] Current task: Initialization +++ Current Phase: Starting [00:00:12] Current task: Initialization +++ Current Phase: Finished [00:00:12] Executing Tcl: synth_design -top x300 -part xc7k410tffg900-2 -verilog_define BUILD_1G=1 -verilog_define BUILD_10G=1 -verilog_define SFP0_1GBE=1 -verilog_define SFP1_10GBE=1 -verilog_define RFNOC=1 -verilog_define X310=1 -verilog_define GIT_HASH=32'hf1b40696 [00:00:12] Starting Synthesis Command CRITICAL WARNING: [Constraints 18-1056] Clock 'FPGA_CLK' completely overrides clock 'FPGA_CLK_p'. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:72] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks ioport2_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:72] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks ioport2_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:73] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks rio40_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:73] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:74] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks radio_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:74] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk_div2]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:75] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks radio_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:75] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks ioport2_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:76] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks IoPort2Wrapperx/RxLowSpeedClk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:76] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:77] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks ce_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:78] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:78] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks ce_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:79] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks radio_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:79] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_10ge.xdc:13] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk_div2]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_10ge.xdc:14] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/RXOUTCLK}]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_10ge.xdc:15] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -filter {NAME =~ *sfpp_io_*/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/*/gtxe2_i/TXOUTCLK}]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_10ge.xdc:16] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_1ge.xdc:13] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_1ge.xdc:14] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_1ge.xdc:15] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_dram.xdc:8] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks mmcm_ps_clk_bufg_in]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_dram.xdc:8] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_dram.xdc:9] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks ddr3_axi_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_dram.xdc:9] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks bus_clk]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_dram.xdc:10] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks ddr3_axi_clk_x2]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/x300_dram.xdc:10] [00:03:56] Current task: Synthesis +++ Current Phase: Starting [00:03:56] Current task: Synthesis +++ Current Phase: RTL Component Statistics [00:03:56] Current task: Synthesis +++ Current Phase: RTL Hierarchical Component Statistics [00:04:08] Current task: Synthesis +++ Current Phase: Part Resource Summary [00:05:16] Current task: Synthesis +++ Current Phase: Cross Boundary and Area Optimization [00:05:20] Current task: Synthesis +++ Current Phase: Applying XDC Timing Constraints [00:05:46] Current task: Synthesis +++ Current Phase: Timing Optimization [00:06:18] Current task: Synthesis +++ Current Phase: Technology Mapping [00:06:18] Current task: Synthesis +++ Current Phase: IO Insertion [00:06:22] Current task: Synthesis +++ Current Phase: Flattening Before IO Insertion [00:06:35] Current task: Synthesis +++ Current Phase: Final Netlist Cleanup [00:06:43] Current task: Synthesis +++ Current Phase: Renaming Generated Instances [00:06:51] Current task: Synthesis +++ Current Phase: Rebuilding User Hierarchy [00:06:54] Current task: Synthesis +++ Current Phase: Renaming Generated Ports [00:06:55] Current task: Synthesis +++ Current Phase: Handling Custom Attributes [00:06:55] Current task: Synthesis +++ Current Phase: Renaming Generated Nets [00:06:58] Current task: Synthesis +++ Current Phase: Writing Synthesis Report [00:06:59] Current task: Synthesis +++ Current Phase: Finished [00:06:59] Translating Synthesized Netlist CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb47'. The XDC file /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb47/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [get_pins int_reset_sync/reset_int*/PRE]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:591] CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [get_pins int_div2_reset_sync/reset_int*/PRE]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:592] CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [get_pins ce_reset_sync/reset_int*/PRE]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:593] CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [get_pins radio_reset_sync/reset_int*/PRE]'. [/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/timing.xdc:594] [00:10:21] Current task: Translating Synthesized Netlist +++ Current Phase: Starting [00:10:21] Current task: Translating Synthesized Netlist +++ Current Phase: Finished [00:10:21] Executing Tcl: report_drc -ruledeck methodology_checks -file /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-X310_RFNOC_HG/methodology.rpt [00:10:21] Starting DRC Command [00:11:06] Current task: DRC +++ Current Phase: Starting [00:11:06] Current task: DRC +++ Current Phase: Finished [00:11:06] Executing Tcl: opt_design -directive NoBramPowerOpt [00:11:06] Starting Logic Optimization Command [00:11:07] Current task: Logic Optimization +++ Current Phase: Starting [00:11:07] Current task: Logic Optimization +++ Current Phase: Finished [00:11:07] Starting DRC Task [00:11:09] Current task: DRC +++ Current Phase: Starting [00:11:09] Current task: DRC +++ Current Phase: Finished [00:11:09] Starting Logic Optimization Task [00:11:19] Current task: Logic Optimization +++ Current Phase: Starting [00:11:28] Current task: Logic Optimization +++ Current Phase: 1 Retarget [00:11:32] Current task: Logic Optimization +++ Current Phase: 2 Constant propagation [00:11:41] Current task: Logic Optimization +++ Current Phase: 3 Sweep [00:11:45] Current task: Logic Optimization +++ Current Phase: 4 BUFG optimization [00:11:52] Current task: Logic Optimization +++ Current Phase: 5 Shift Register Optimization [00:11:52] Current task: Logic Optimization +++ Current Phase: Finished [00:11:52] Starting Connectivity Check Task [00:11:57] Current task: Connectivity Check +++ Current Phase: Starting [00:11:57] Current task: Connectivity Check +++ Current Phase: Finished [00:11:57] Executing Tcl: place_design -directive ExtraNetDelay_high [00:11:57] Starting Placer Command [00:12:15] Current task: Placer +++ Current Phase: Starting [00:12:15] Starting Placer Task [00:12:15] Current task: Placer +++ Current Phase: Starting [00:12:15] Current task: Placer +++ Current Phase: 1 Placer Initialization [00:12:34] Current task: Placer +++ Current Phase: 1.1 Placer Initialization Netlist Sorting [00:13:16] Current task: Placer +++ Current Phase: 1.2 IO Placement/ Clock Placement/ Build Placer Device [00:13:43] Current task: Placer +++ Current Phase: 1.3 Build Placer Netlist Model [00:13:44] Current task: Placer +++ Current Phase: 1.4 Constrain Clocks/Macros [00:15:47] Current task: Placer +++ Current Phase: 2 Global Placement [00:15:47] Current task: Placer +++ Current Phase: 3 Detail Placement [00:16:19] Current task: Placer +++ Current Phase: 3.1 Commit Multi Column Macros [00:16:20] Current task: Placer +++ Current Phase: 3.3 Area Swap Optimization [00:16:21] Current task: Placer +++ Current Phase: 3.4 Pipeline Register Optimization [00:16:21] Current task: Placer +++ Current Phase: 3.5 Timing Path Optimizer [00:16:22] Current task: Placer +++ Current Phase: 3.6 Fast Optimization [00:17:13] Current task: Placer +++ Current Phase: 3.7 Small Shape Detail Placement [00:17:14] Current task: Placer +++ Current Phase: 3.9 Pipeline Register Optimization [00:17:17] Current task: Placer +++ Current Phase: 3.10 Fast Optimization [00:17:26] Current task: Placer +++ Current Phase: 4.1 Post Commit Optimization [00:17:27] Current task: Placer +++ Current Phase: 4.1.1 Post Placement Optimization [00:20:25] Current task: Placer +++ Current Phase: 4.1.1.1 BUFG Insertion [00:20:26] Current task: Placer +++ Current Phase: 4.2 Post Placement Cleanup [00:20:27] Current task: Placer +++ Current Phase: 4.3 Placer Reporting [00:20:31] Current task: Placer +++ Current Phase: 4.4 Final Placement Cleanup [00:20:32] Current task: Placer +++ Current Phase: Finished [00:20:32] Executing Tcl: phys_opt_design -directive AggressiveExplore [00:20:32] Starting Physical Synthesis Command [00:20:54] Current task: Physical Synthesis +++ Current Phase: Starting [00:20:54] Starting Physical Synthesis Task [00:20:54] Current task: Physical Synthesis +++ Current Phase: Starting [00:21:13] Current task: Physical Synthesis +++ Current Phase: 1 Physical Synthesis Initialization [00:21:14] Current task: Physical Synthesis +++ Current Phase: 2 Fanout Optimization [00:21:14] Current task: Physical Synthesis +++ Current Phase: 3 Placement Based Optimization [00:21:15] Current task: Physical Synthesis +++ Current Phase: 4 Rewire [00:21:15] Current task: Physical Synthesis +++ Current Phase: 5 Critical Cell Optimization [00:21:16] Current task: Physical Synthesis +++ Current Phase: 6 Fanout Optimization [00:21:16] Current task: Physical Synthesis +++ Current Phase: 7 Placement Based Optimization [00:21:16] Current task: Physical Synthesis +++ Current Phase: 8 Rewire [00:21:17] Current task: Physical Synthesis +++ Current Phase: 9 Critical Cell Optimization [00:21:17] Current task: Physical Synthesis +++ Current Phase: 10 Fanout Optimization [00:21:18] Current task: Physical Synthesis +++ Current Phase: 11 Placement Based Optimization [00:21:18] Current task: Physical Synthesis +++ Current Phase: 12 Rewire [00:21:19] Current task: Physical Synthesis +++ Current Phase: 13 Critical Cell Optimization [00:21:19] Current task: Physical Synthesis +++ Current Phase: 14 DSP Register Optimization [00:21:19] Current task: Physical Synthesis +++ Current Phase: 15 BRAM Register Optimization [00:21:20] Current task: Physical Synthesis +++ Current Phase: 16 URAM Register Optimization [00:21:20] Current task: Physical Synthesis +++ Current Phase: 17 Shift Register Optimization [00:21:21] Current task: Physical Synthesis +++ Current Phase: 18 DSP Register Optimization [00:21:21] Current task: Physical Synthesis +++ Current Phase: 19 BRAM Register Optimization [00:21:22] Current task: Physical Synthesis +++ Current Phase: 20 URAM Register Optimization [00:21:22] Current task: Physical Synthesis +++ Current Phase: 21 Shift Register Optimization [00:21:23] Current task: Physical Synthesis +++ Current Phase: 22 Critical Pin Optimization [00:21:50] Current task: Physical Synthesis +++ Current Phase: 23 Very High Fanout Optimization [00:21:50] Current task: Physical Synthesis +++ Current Phase: 24 Placement Based Optimization [00:21:51] Current task: Physical Synthesis +++ Current Phase: 25 Critical Path Optimization [00:22:01] Current task: Physical Synthesis +++ Current Phase: 26 BRAM Enable Optimization [00:22:01] Current task: Physical Synthesis +++ Current Phase: Finished [00:22:01] Executing Tcl: route_design -directive Explore -tns_cleanup [00:22:01] Starting Routing Command [00:22:21] Current task: Routing +++ Current Phase: Starting [00:22:21] Starting Routing Task [00:22:22] Current task: Routing +++ Current Phase: Starting [00:22:50] Current task: Routing +++ Current Phase: 1 Build RT Design [00:22:50] Current task: Routing +++ Current Phase: 2 Router Initialization [00:22:51] Current task: Routing +++ Current Phase: 2.1 Create Timer [00:22:52] Current task: Routing +++ Current Phase: 2.2 Fix Topology Constraints [00:23:02] Current task: Routing +++ Current Phase: 2.3 Pre Route Cleanup [00:23:37] Current task: Routing +++ Current Phase: 2.4 Update Timing [00:23:37] Current task: Routing +++ Current Phase: 2.5 Update Timing for Bus Skew [00:23:41] Current task: Routing +++ Current Phase: 2.5.1 Update Timing [00:24:00] Current task: Routing +++ Current Phase: 3 Initial Routing [00:24:57] Current task: Routing +++ Current Phase: 4.1 Global Iteration 0 [00:25:17] Current task: Routing +++ Current Phase: 4.2 Global Iteration 1 [00:25:17] Current task: Routing +++ Current Phase: 5 Delay and Skew Optimization [00:25:17] Current task: Routing +++ Current Phase: 5.1 TNS Cleanup [00:25:17] Current task: Routing +++ Current Phase: 5.1.1 Delay CleanUp [00:25:18] Current task: Routing +++ Current Phase: 5.2 Clock Skew Optimization [00:25:18] Current task: Routing +++ Current Phase: 6 Post Hold Fix [00:25:18] Current task: Routing +++ Current Phase: 6.1 Hold Fix Iter [00:25:25] Current task: Routing +++ Current Phase: 6.1.1 Update Timing [00:25:25] Current task: Routing +++ Current Phase: 7 Timing Verification [00:25:31] Current task: Routing +++ Current Phase: 7.1 Update Timing [00:25:32] Current task: Routing +++ Current Phase: 8 Route finalize [00:25:32] Current task: Routing +++ Current Phase: 9 Verifying routed nets [00:25:41] Current task: Routing +++ Current Phase: 10 Depositing Routes [00:25:58] Current task: Routing +++ Current Phase: 11 Post Router Timing [00:25:58] Current task: Routing +++ Current Phase: Finished [00:25:58] Executing Tcl: phys_opt_design -directive Explore [00:25:58] Starting Physical Synthesis Command [00:27:42] Current task: Physical Synthesis +++ Current Phase: Starting [00:27:42] Current task: Physical Synthesis +++ Current Phase: Finished [00:27:42] Executing Tcl: report_power -file /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-X310_RFNOC_HG/post_route_power.rpt [00:27:42] Starting Power Reporting Command [00:28:02] Current task: Power Reporting +++ Current Phase: Starting [00:28:02] Current task: Power Reporting +++ Current Phase: Finished [00:28:02] Executing Tcl: report_drc -file /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-X310_RFNOC_HG/post_imp_drc.rpt [00:28:02] Starting DRC Command [00:28:30] Current task: DRC +++ Current Phase: Starting [00:28:31] Current task: DRC +++ Current Phase: Finished [00:28:31] Executing Tcl: write_bitstream -force /home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300/build-X310_RFNOC_HG/x300.bit [00:28:31] Starting Write Bitstream Command CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design contains one or more evaluation cores that will cease to function after a certain period of time. This design should NOT be used in production systems. [00:29:47] Current task: Write Bitstream +++ Current Phase: Starting [00:29:47] Current task: Write Bitstream +++ Current Phase: Finished [00:29:47] Process terminated. Status: Success ======================================================== Warnings: 948 Critical Warnings: 37 Errors: 0 make[1]: Leaving directory '/home/palindrome/workarea-rfnoc/uhd/fpga-src/usrp3/top/x300' Exporting bitstream files... Generating LVBITX... Exporting build report... Build DONE ... X310_RFNOC_HG