<div dir="ltr"><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Great, thank you for the clarification, Derek.<br><br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Regards,<br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Brais.<br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)"><br><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">2017-10-26 17:58 GMT+02:00 Derek Kozel <span dir="ltr"><<a href="mailto:derek.kozel@ettus.com" target="_blank">derek.kozel@ettus.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><div><div><div>Hello Brais,<br><br></div>Sorry for the long delay. Yes, the B210 has a Spartan 6 which is not supported by Vivado so the design uses ISE. This, and the smaller size of the B210's FPGA, is why RFNoC support has not been added to it. All third generation USRPs support RFNoC and so will all planned future USRPs.<br><br></div>I hope your project is going well and that it is a success.<br><br></div>Regards,<br></div>Derek<br></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Oct 3, 2017 at 6:22 PM, Brais Ares <span dir="ltr"><<a href="mailto:bares@gradiant.org" target="_blank">bares@gradiant.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Thank you Derek, <br><br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">I was playing around with E300 design, but we actually need to use B2X0 devices, apparently not supported by RFNoC. Also we need to implement some complex decimation and filtering so that FIR block will not be enough.<br><br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">I guess, if I'm not mistaken, our only choice is to use Xilinx ISE to modify the hdl design.<br><br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Regards,<br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Brais.<br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)"></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)"><br><br></div></div><div class="gmail_extra"><div><div class="m_-8539267260749334513h5"><br><div class="gmail_quote">2017-10-03 12:45 GMT+02:00 Derek Kozel <span dir="ltr"><<a href="mailto:derek.kozel@ettus.com" target="_blank">derek.kozel@ettus.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><div><div><div><div>Hello Brais,<br><br></div>The HDL design does have a top block and is composed of usefully divided sub blocks. It is not however designed using the graphical Vivado workflow, but a source based one. Here is the top block:<br><a href="https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/e300/e310.v" target="_blank">https://github.com/EttusResear<wbr>ch/fpga/blob/maint/usrp3/top/e<wbr>300/e310.v</a><br><br></div>Your application however sounds exactly like what the RFNoC architecture was designed for. This architecture, which the E310 implements, allows you to add in a self contained block of functional logic wrapped by an interface supplied by Ettus. I recommend reading this application note and possibly watching this video which introduces the architecture and leads through the creation of a sample RFNoC block.<br><br><a href="https://kb.ettus.com/Getting_Started_with_RFNoC_Development" target="_blank">https://kb.ettus.com/Getting_S<wbr>tarted_with_RFNoC_Development</a><br><a href="https://www.youtube.com/watch?v=j-EfyPVpaJ8" target="_blank">https://www.youtube.com/watch?<wbr>v=j-EfyPVpaJ8</a><br><br></div>If you only want to add a filter or two there is already an FIR block which you could either directly make use of or make hopefully minor modifications to meet your needs.<br><a href="https://github.com/EttusResearch/fpga/blob/6996ed662e5ae170e60ab8cb6de54c362cecf8d2/usrp3/lib/rfnoc/noc_block_fir_filter.v#L141" target="_blank">https://github.com/EttusResear<wbr>ch/fpga/blob/6996ed662e5ae170e<wbr>60ab8cb6de54c362cecf8d2/usrp3/<wbr>lib/rfnoc/noc_block_fir_filter<wbr>.v#L141</a><br><br></div>Regards,<br></div>Derek<br><div><div><div><br></div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote"><div><div class="m_-8539267260749334513m_-1459528716491462273h5">On Thu, Sep 21, 2017 at 4:48 PM, Brais Ares via USRP-users <span dir="ltr"><<a href="mailto:usrp-users@lists.ettus.com" target="_blank">usrp-users@lists.ettus.com</a>></span> wrote:<br></div></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div><div class="m_-8539267260749334513m_-1459528716491462273h5"><div dir="ltr"><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Hello,<br><br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">We want to add some blocks to HDL design in E310 device. We followed the instructions to build Vivado project and it worked okay.</div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)"><br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Thing is the built design when opened in Vivado looks <a href="https://www.dropbox.com/s/5w7ari9xlpth4e9/hdl_hierarchy.JPG?dl=0" target="_blank">this way</a> ... where design sources hierarchy is kind of complex. I was expecting a top module or at least not that much sources.<br><br></div><div class="gmail_default" style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)">Is there no way to see the design as a block design (like in a typical Vivado workflow)? <br><br>Adding just a few filters to this design implies reverse-engineering what is going on in most of these source files...<br clear="all"></div><br><div style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)" class="gmail_default">​Any advice in how to proceed/start is appreciated.<br></div><div style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)" class="gmail_default">Regards,<br></div><div style="font-family:trebuchet ms,sans-serif;color:rgb(0,0,0)" class="gmail_default">Brais.​</div><br></div>
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