<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Okay. Thanks, Marcus.<div class=""><br class=""></div><div class="">I appreciate you digging into the code and providing the referenced filename.</div><div class=""><br class=""></div><div class="">From your description, it appears to be a first-order update, nothing too fancy, but run fast enough that it’s pretty good.</div><div class=""><br class=""></div><div class="">You also anticipate the next step and I agree that there’s no real need to sample continuously. Rather, as you suggest, it would be good enough to every so often sample the set point (correction value) via the UHD and cache the value on the host. Then at boot, if there is no 1 PPS reference, write that value back to the USRP FPGA’s DAC register. I may be making things up a little having not looked at the code, but that’s the general idea, and what I have done in the past with other systems.</div><div class=""><br class=""></div><div class="">It’s a little bit academic and there are other solutions, like driving the reference input with 1 PPS derived from a GPSDO that has high stability (stratum-3), for example.</div><div class=""><br class=""></div><div class="">I think I have plenty to go on now and thank you for the quick response.</div><div class=""><br class=""></div><div class="">Steven</div><div class=""><br class=""></div><div class=""><br class=""><div class="">
<div class=""><div class=""><font class="Apple-style-span" face="'Marker Felt'" size="3"><span class="Apple-style-span" style="font-size: 12px;">Steven Knudsen, Ph.D., P.Eng.</span></font></div><div class=""><div style="margin: 0px;" class=""><font class="Apple-style-span" face="'Marker Felt'">www.</font><font class="Apple-style-span" face="'Marker Felt'"> </font><font class="Apple-style-span" face="'Marker Felt'"><a href="http://techconficio.ca" class="">techconficio.ca</a></font></div></div><div style="orphans: 2; widows: 2; margin: 0px;" class=""><span class="Apple-style-span" style="font-family: 'Marker Felt';"><a href="http://www.linkedin.com/in/knudstevenknudsen" class="">www.linkedin.com/in/knudstevenknudsen</a></span></div><div style="orphans: 2; widows: 2; margin: 0px;" class=""><br class=""></div><div style="orphans: 2; widows: 2; margin: 0px;" class=""><font color="#800000" face="Kristen ITC" size="1" class=""><i class="">Der entscheidende Augenblick der menschlichen Entwicklung ist immerwährend. Darum sind die revolutionären geistigen Bewegungen, welche alles Frühere für nichtig erklären, im Recht, denn es ist noch nichts geschehen. - Franz Kafka</i></font></div></div>
</div>
<br class=""><div><blockquote type="cite" class=""><div class="">On Mar 29, 2016, at 05:17, Marcus Müller via USRP-users <<a href="mailto:usrp-users@lists.ettus.com" class="">usrp-users@lists.ettus.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class="">
  
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    Hi steven,<br class="">
    <blockquote type="cite" class="">is whether or not the DAC setting for the
      VCTCXO is saved periodically</blockquote>
    Hm, what do you mean with "saved"? Saved as in "stored somewhere for
    later analysis"?<br class="">
    <br class="">
    No; the value is updated continously, whether there is an active PPS
    signal or there just was one (which isn't active anymore).<br class="">
    <br class="">
    I had to read Verilog myself, since I didn't want to give you false
    information, but: <br class="">
    usrp3/top/b205/b205_ref_pll.v has a state machine.<br class="">
    Lines 78-100: Assuming you're in the state "ref_detected",
    "ref_is_pps" = 1, ref_is_10M = 0, but then, the PPS pulses stop,
    nothing will change the state; the transition only happens when
    there's a rising PPS edge, but it's too early or too late.<br class="">
    So, "valid_ref" is 1, at least until the next PPS pulse comes; if
    that comes in time, yay, we get to gradually adjust the externa<br class="">
    Lines 193-255: since valid_ref==1, and ref_is_pps==1, you're in a
    loop between states<br class="">
MEASURE->CAPTURE->CALCULATE_ERROR->CALCULATE_ADJUSTMENT->CALCULATE_OUTPUT_VALUE->APPLY_OUTPUT_VALUE->MEASURE<br class="">
    <br class="">
    So what happens here is based on the continously running PLL chip's
    internal clocks, an adjustment for the VCO is calculated and
    applied. So yes, the DAC value is continously kept during operation,
    but no, they're not sent to the host computer for analysis.<br class="">
    <br class="">
    Adding another stream that would be "continously sampled" from these
    values would be rather intense, but you could go ahead and just add
    a UHD user settings register, so that you can, by adding a method to
    UHD somewhere, read it from the host computer periodically. Maybe
    easier: "tapping" the lines running to the DAC by also feeding them
    to the GPIO port, and monitoring those with e.g. a logic analyser
    device or any SPI-to-USB converter that works with the 12.5MHz SPI
    clock; or, instead, because you're already modifying the FPGA, just
    outputting the calculated errors/adjustment values/... to the GPIO
    in whatever format you please (e.g. either as parallel bus values,
    or by using instantiating another SPI driver module). <br class="">
    <br class="">
    Best regards,<br class="">
    Marcus<br class="">
    <br class="">
    <br class="">
    <div class="moz-cite-prefix">On 29.03.2016 05:28, Steven Knudsen via
      USRP-users wrote:<br class="">
    </div>
    <blockquote cite="mid:5753EBFC-A80A-4F27-9BBE-7E972BE2822C@ieee.org" type="cite" class="">
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      Thanks very much for the confirmation. 
      <div class=""><br class="">
      </div>
      <div class="">And thanks for opting for the really stable option. </div>
      <div class=""><br class="">
      </div>
      <div class="">I am looking at details for holdover when 1 PPS is
        not available. This is relevant to TDMA systems, among other
        things.</div>
      <div class=""><br class="">
      </div>
      <div class="">An obvious question that the list or Ettus may be
        able to help with, and that saves me looking into the FPGA
        source, is whether or not the DAC setting for the VCTCXO is
        saved periodically while there is an external reference? I hope
        so :-)  I am assuming there is a simple control loop for the DAC
        value, guessing a PID or something.</div>
      <div class=""><br class="">
      </div>
      <div class="">I recently had to develop a comparable clock
        discipline subsystem for a radio that was being refitted with
        digital technologies and that would be expected to operate with
        or without GPS and support ranges in excess of 30 km. Loads of
        fun.</div>
      <div class=""><br class="">
      </div>
      <div class="">Thanks again for the quick response!</div>
      <div class=""><br class="">
      </div>
      <div class="">steven</div>
      <div class=""><br class="">
      </div>
      <div class=""><br class="">
        <div class="">
          <div class="">
            <div class=""><font class="Apple-style-span" face="'Marker
                Felt'" size="3"><span class="Apple-style-span" style="font-size: 12px;">Steven Knudsen, Ph.D., P.Eng.</span></font></div>
            <div class="">
              <div style="margin: 0px;" class=""><font class="Apple-style-span" face="'Marker Felt'">www.</font><font class="Apple-style-span" face="'Marker Felt'"> </font><font class="Apple-style-span" face="'Marker Felt'"><a moz-do-not-send="true" href="http://techconficio.ca/" class="">techconficio.ca</a></font></div>
            </div>
            <div style="orphans: 2; widows: 2; margin: 0px;" class=""><span class="Apple-style-span" style="font-family: 'Marker
                Felt';"><a moz-do-not-send="true" href="http://www.linkedin.com/in/knudstevenknudsen" class="">www.linkedin.com/in/knudstevenknudsen</a></span></div>
            <div style="orphans: 2; widows: 2; margin: 0px;" class=""><br class="">
            </div>
            <div style="orphans: 2; widows: 2; margin: 0px;" class=""><font class="" face="Kristen ITC" color="#800000" size="1"><i class="">Der entscheidende Augenblick der
                  menschlichen Entwicklung ist immerwährend. Darum
                  sind die revolutionären geistigen Bewegungen, welche
                  alles Frühere für nichtig erklären, im Recht, denn es
                  ist noch nichts geschehen. - Franz Kafka</i></font></div>
          </div>
        </div>
        <br class="">
        <div class="">
          <blockquote type="cite" class="">
            <div class="">On Mar 28, 2016, at 17:14, Derek Kozel <<a moz-do-not-send="true" href="mailto:derek.kozel@ettus.com" class=""></a><a class="moz-txt-link-abbreviated" href="mailto:derek.kozel@ettus.com">derek.kozel@ettus.com</a>>
              wrote:</div>
            <br class="Apple-interchange-newline">
            <div class="">
              <div dir="ltr" class="">
                <div class="">
                  <div class="">
                    <div class="">Hello Steven,<br class="">
                      <br class="">
                    </div>
                    The onboard reference is a VCTCXO indeed made by
                    CTS, you've found the right datasheet. It is the
                    0.5ppm version.<br class="">
                    <br class="">
                  </div>
                  Regards,<br class="">
                </div>
                Derek<br class="">
              </div>
              <div class="gmail_extra"><br class="">
                <div class="gmail_quote">On Mon, Mar 28, 2016 at 3:57
                  PM, Steven Knudsen via USRP-users <span dir="ltr" class=""><<a moz-do-not-send="true" href="mailto:usrp-users@lists.ettus.com" target="_blank" class="">usrp-users@lists.ettus.com</a>></span>
                  wrote:<br class="">
                  <blockquote class="gmail_quote" style="margin:0 0 0
                    .8ex;border-left:1px #ccc solid;padding-left:1ex">
                    <div style="word-wrap:break-word" class="">I may be
                      blind, but I have not found a document reference
                      for the clock on the B200mini. However, from the
                      markings on the clock I think it’s a CTS VTCXO
                      matching the link to the data sheet below. Can
                      anyone confirm this and if so, the stability
                      grade?
                      <div class=""><br class="">
                      </div>
                      <div class=""><a moz-do-not-send="true" href="http://www.ctscorp.com/wp-content/uploads/2015/11/008-0371-0.pdf" target="_blank" class="">http://www.ctscorp.com/wp-content/uploads/2015/11/008-0371-0.pdf</a></div>
                      <div class=""><br class="">
                      </div>
                      <div class="">thanks!</div>
                      <div class=""><br class="">
                      </div>
                      <div class="">steven</div>
                      <div class=""><br class="">
                      </div>
                      <div class=""><br class="">
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                                                    <div class=""><span class="">
                                                        <div class=""><font class="" face="'Marker
                                                          Felt'" size="3"><span style="font-size:12px" class="">Steven Knudsen, Ph.D., P.Eng.</span></font></div>
                                                        <div class=""><span style="font-size:12px" class="">
                                                          <div style="margin-top:0px;margin-right:0px;margin-bottom:0px;margin-left:0px" class=""><font class="" face="'Marker
                                                          Felt'">www.</font><font class="" face="'Marker
                                                          Felt'"> </font><font class="" face="'Marker
                                                          Felt'"><a moz-do-not-send="true" href="http://techconficio.ca/" target="_blank" class="">techconficio.ca</a></font></div>
                                                          </span></div>
                                                      </span>
                                                      <div style="margin:
                                                        0px;" class=""><span style="font-family:'Marker
                                                          Felt'" class=""><a moz-do-not-send="true" href="http://www.linkedin.com/in/knudstevenknudsen" target="_blank" class=""></a><a class="moz-txt-link-abbreviated" href="http://www.linkedin.com/in/knudstevenknudsen">www.linkedin.com/in/knudstevenknudsen</a></span></div>
                                                      <div style="margin:
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                                                      </div>
                                                      <div style="margin:
                                                        0px;" class=""><span style="color:rgb(128,0,0);font-family:'Kristen
ITC';font-size:10px;font-style:italic" class="">All the wires are cut,
                                                          my friends<br class="">
                                                          Live beyond
                                                          the severed
                                                          ends.  Louis
                                                          MacNeice</span></div>
                                                    </div>
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                    <br class="">
                    _______________________________________________<br class="">
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