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<p class="MsoNormal">I’ve seen a few threads discussing various options for bringing out a signal to control an external Tx/Rx switch with a B210. A couple suggestions were to use a debug pin through the MICTOR connector or an unused debug UART pin. Both seemed
 to require FPGA modifications. Has anybody made headway with this? There was also talk of UHD firmware binaries including something like this as a feature.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">If there’s nothing like this supported out-of-the-box, we can make some FPGA changes. What I’d like to know is:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo1"><![if !supportLists]><span style="mso-list:Ignore">1)<span style="font:7.0pt "Times New Roman"">     
</span></span><![endif]>What changes would have to be made? Is it as simple as toggling an output pin based on a TX/RX/IDLE signal in the FPGA code (I think this logic is called “ATR”)?<o:p></o:p></p>
<p class="MsoListParagraph"><o:p> </o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo1"><![if !supportLists]><span style="mso-list:Ignore">2)<span style="font:7.0pt "Times New Roman"">     
</span></span><![endif]>What kind of delay can we expect between when this signal is active and when RF is actually being modulated over the air? If I understand correctly, this signal is driven by whether samples are present in the TX buffer. It sounds like
 we would have to account for delays due to the DSP chain and RF frontend. Is this understanding correct? We could probably measure and calibrate that out. However, what happens if we are using timed bursts? Does the TX signal only go active once the scheduled
 time is reached?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoListParagraph" style="text-indent:-.25in;mso-list:l0 level1 lfo1"><![if !supportLists]><span style="mso-list:Ignore">3)<span style="font:7.0pt "Times New Roman"">     
</span></span><![endif]>What voltage level is brought out to the UART pins? Is it 3.3V?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Aside from FPGA, can we pull this signal from tx_enable that is driving the status LEDs?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Best regards,<o:p></o:p></p>
<p class="MsoNormal">Sean Nowlan<o:p></o:p></p>
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