[USRP-users] Issues generating and loading bitstreams with RFNoC blocks (UHD-3.15.LTS)

Jorge Arroyo Giganto jarroyo at gradiant.org
Wed Jul 29 16:41:23 EDT 2020


Hi Rob,

After a while understanding how uhd_image_builder.py works, I couldn't
figure out a way to fix the "create_oot_include" function, but I managed to
make uhd_image_builder.py find my OOT block (noc_block_gain.v). Maybe it's
not the most elegant way to do it, but it worked for me.

I copied my noc_block_gain.v file (after making sure it passed the
testbench) to the /uhd-fpga/usrp3/lib/rfnoc folder, and added the following
line to the Makefile.srcs from that same folder, in the same way the other
blocks are added:
        noc_block_gain.v \

After doing that, I was able to successfully generate my bitstream with
'./uhd_image_builder.py gain fft -I ~/rfnoc_UHD315/src/rfnoc-tutorial -d
e31x -t E310_RFNOC -m 3 --fill-with-fifos'.

Also, in case it's useful, I was also able to fix the uhd_image_loader
issue I mentioned I had with the E310, changing the IP address to localhost
worked just fine (--args="type=e3xx,addr=127.0.0.1").

Thank you for your help,

Jorge


El mar., 28 jul. 2020 a las 17:33, Rob Kossler (<rkossler at nd.edu>) escribió:

> so, the problem is that uhd_image_builder.py still can't find your OOT noc
> block (error: module not found)?
>
> This file looks for several methods for including your OOT block.  I think
> it first looks for a Makefile.inc if it exists in your OOT 'rfnoc' folder.
> If it doesn't find that, it looks for perhaps the same file in your
> 'rfnoc/fpga-src' folder.  And, if not that looks for the file Makefile.srcs
> in that folder.  I'm sure I don't have it exactly right, but perhaps just
> look at uhd_image_builder.py to see the logic in the "create_oot_include"
> function.  Somehow, it seems it is not finding your block.  If you have no
> luck with Makefile.srcs, you could try adding Makefile.inc to various
> folders.
>
> Rob
>
> On Tue, Jul 28, 2020 at 11:25 AM Jorge Arroyo Giganto <
> jarroyo at gradiant.org> wrote:
>
>> Hi Rob,
>>
>> Thanks a lot for your patch file, but unfortunately I'm still getting the
>> same errors when trying to use custom RFNoC blocks with
>> uhd_image_builder.py.
>>
>> Any other help would be greatly appreciated,
>>
>> Jorge
>>
>> El mar., 28 jul. 2020 a las 15:56, Rob Kossler (<rkossler at nd.edu>)
>> escribió:
>>
>>> Try this patch file.  I received from Ettus a long time ago (Oct 2019?)
>>> but it appears that it is still not fixed.
>>> Rob
>>>
>>> On Tue, Jul 28, 2020 at 6:27 AM Jorge Arroyo Giganto via USRP-users <
>>> usrp-users at lists.ettus.com> wrote:
>>>
>>>> Hi,
>>>>
>>>>
>>>> I’m working on getting a solid workflow to build and use RFNoC blocks.
>>>> I’m using branches UHD-3.15.LTS and GNU Radio’s maint-3.7 (also, packet
>>>> gr-ettus from the master branch and uhd-fpga from the UHD-3.15.LTS branch).
>>>> I’m using an E310 (SG1), with the SD image I get with
>>>> ‘uhd_images_downloader -t e310 -t sdimg’ (usrp_e310_fs.sdimg). Also, I’m
>>>> running Ubuntu 18.04 and I’ve got Vivado 2018.3 installed.
>>>>
>>>> A couple of weeks ago I started trying to follow the ‘Getting Started
>>>> with RFNoC Development’ guide, and tried using rfnoc-devel and master
>>>> branches, but it seems like this UHD-3.15.LTS is the one working the best
>>>> for me, but I still have some issues.
>>>>
>>>> Following the guide, I built a custom block (gain), which I was able to
>>>> get through the testbench (after quite a bit of attempts), but when trying
>>>> to generate a bitstream (.bit file) with my gain block I got the following
>>>> errors:
>>>>
>>>>
>>>>     ~/rfnoc_UHD315/src/uhd-fpga/usrp3/tools/scripts$
>>>> ./uhd_image_builder.py gain fft -I ~/rfnoc_UHD315/src/rfnoc-tutorial/ -d
>>>> e31x -t E310_RFNOC -m 4 –fill-with-fifos
>>>>
>>>>      .
>>>>
>>>>      .
>>>>
>>>>      .
>>>>
>>>>      ERROR: [Synth 8-439] module 'noc_block_gain' not found
>>>> [/home/jarroyo/rfnoc_UHD315/
>>>> src/uhd-fpga/usrp3/top/e31x/rfnoc_ce_auto_inst_e31x.v:20]
>>>>
>>>>      ERROR: [Synth 8-6156] failed synthesizing module 'e31x_core'
>>>> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x_core.v:17]
>>>>
>>>>      ERROR: [Synth 8-6156] failed synthesizing module 'e31x'
>>>> [/home/jarroyo/rfnoc_UHD315/src/uhd-fpga/usrp3/top/e31x/e31x.v:13]
>>>>
>>>>      [00:01:46] Current task: Synthesis +++ Current Phase: Starting
>>>>
>>>>      ERROR: [Common 17-69] Command failed: Synthesis failed - please
>>>> see the console or run log file for details
>>>>
>>>>      [00:01:46] Current task: Synthesis +++ Current Phase: Finished
>>>>
>>>>      [00:01:46] Process terminated. Status: Failure
>>>>
>>>>
>>>> If it is useful information, I was able to successfully generate a
>>>> bitstream with existing RFNoC blocks (‘./uhd_image_builder.py window fft -d
>>>> e31x -t E310_RFNOC -m 3 –fill-with-fifos’ for example, is working), so
>>>> that’s why I guess my main issue is with the gain custom block.
>>>>
>>>>
>>>> Also, another issue I’m having is using uhd_image_loader on the E310
>>>> terminal when loading my own bitstreams:
>>>>
>>>>
>>>>      root at ni-e31x:~# uhd_image_loader
>>>> --args="type=e3xx,addr=192.168.10.2" --fpga-path
>>>> /usr/share/uhd/images/e31x.bit
>>>>
>>>>      [INFO] [UHD] linux; GNU C++ version 8.2.0; Boost_106800;
>>>> UHD_3.15.0.0-0-gaea0e2de
>>>>
>>>>      No applicable UHD devices found
>>>>
>>>>
>>>> Is there anything I might be doing wrong? Or is this workflow with
>>>> these branches and tool versions not the most appropiate currently?
>>>>
>>>>
>>>> Thanks in advance,
>>>>
>>>>
>>>> Jorge
>>>> _______________________________________________
>>>> USRP-users mailing list
>>>> USRP-users at lists.ettus.com
>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>>
>>>
>>
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