[USRP-users] Sync problem in custom DUC

Jonathon Pendlum jonathon.pendlum at ettus.com
Sat Jul 18 01:26:31 EDT 2020


Hi Carlos,

Can you try replacing the DmaFIFO block with two FIFO blocks?

Jonathon

On Fri, Jul 17, 2020 at 5:28 AM Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo at gmail.com> wrote:

> Hi Jonathon,
>
> Thanks for the reply. This is my simplest test:
>
> [image: sample_0.png]
> At the beginning it works fine, the output is the sum of the two signals:
>
>
> [image: rec_0.png]
>
> But after a while I think the channels are out of sync and the signal is
> weird:
>
> [image: rec_1.png]
>
>
>
>
> El lun., 13 jul. 2020 a las 22:01, Jonathon Pendlum (<
> jonathon.pendlum at ettus.com>) escribió:
>
>> Hi Carlos,
>>
>> Where are the sine waves coming from / how are they generated? What is
>> your entire flowgraph? What sampling rate are you running at?
>>
>> Jonathon
>>
>> On Fri, Jul 10, 2020 at 2:45 PM Carlos Alberto Ruiz Naranjo via
>> USRP-users <usrp-users at lists.ettus.com> wrote:
>>
>>> This is the code for the adder (between dds_timed and axi_wrapper):
>>>
>>> assign s_axis_data_tvalid2[0] = s_axis_data_tvalid[1] &
>>> s_axis_data_tvalid[0];
>>> assign s_axis_data_tvalid2[1] = s_axis_data_tvalid[1] &
>>> s_axis_data_tvalid[0];
>>>
>>> assign s_axis_data_tuser2 = s_axis_data_tuser;
>>>
>>> assign s_axis_data_tlast2[0] = s_axis_data_tlast[0];
>>> assign s_axis_data_tlast2[1] = s_axis_data_tlast[1];
>>>
>>> assign s_axis_data_tdata2[15: 0] = s_axis_data_tdata[47:32] +
>>> s_axis_data_tdata[15: 0];
>>> assign s_axis_data_tdata2[31:16] = s_axis_data_tdata[63:48] +
>>> s_axis_data_tdata[31:16];
>>>
>>> assign s_axis_data_tready_aux = ~|(~{s_axis_data_tready_out[0
>>> ],s_axis_data_tready_out[1]} & 2'b11);
>>> assign s_axis_data_tready[0] = s_axis_data_tvalid[0] &
>>> s_axis_data_tvalid[1] & s_axis_data_tready_aux;
>>> assign s_axis_data_tready[1] = s_axis_data_tvalid[0] &
>>> s_axis_data_tvalid[1] & s_axis_data_tready_aux;
>>>
>>> El vie., 10 jul. 2020 a las 11:59, Carlos Alberto Ruiz Naranjo (<
>>> carlosruiznaranjo at gmail.com>) escribió:
>>>
>>>> Hi,
>>>>
>>>> I'm customizing the DUC block to do it 2input:1output
>>>>
>>>> input 0  ---> DUC --->
>>>>                                       add ---> output
>>>> input 1  ---> DUC --->
>>>>
>>>> I have added an addsub module between dds_timed and axi_wrapper.
>>>> Apparently it works fine. I can see two tones in the output if the inputs
>>>> are 2 tones.
>>>>
>>>> But I have a synchronization problem. If input_0 is a sine and input_1
>>>> is a sine with pi phase the output should be 0. And the output is 0, but
>>>> after a while (3 minutes) no. I think that the channels are out of sync
>>>> before the adder.
>>>>
>>>> Any idea about what is happening?
>>>>
>>>> Thank you :)
>>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>
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