[USRP-users] Default RFNoC image for N310 does not compile

Rob Kossler rkossler at nd.edu
Fri Jan 31 11:29:13 EST 2020


The issue is solved now.  At first I didn't realize that the patch was
related to the build of the DDR IP component, so when I rebuilt without
clean-ing, the DDR output files were not re-built.  I deleted the DDR IP
folder in the build-ip folder and re-ran the build and now it is past the
point where the error occurred.  Sorry for the false alarm.
Rob

On Thu, Jan 30, 2020 at 3:43 PM Rob Kossler <rkossler at nd.edu> wrote:

> Hi Nate,
> I encountered the "Conflicting VCC voltages in bank 32" error while trying
> to build an N310 XG RFNOC image on v3.15.0.0 and noticed your user's list
> email below which indicated that Vivado 2018.3 requires patch AR71898 in
> order to overcome a bug causing this error. However, after installing the
> patch I am still getting the error.  Perhaps the patch is not installed
> correctly, but the build log file (see snippets below) seems to indicate
> that it is. The second line in the log file shows "# Vivado v2018.3_AR71898
> (64-bit)" which to me indicates that it sees the patch. However, you will
> find the build error mentioned above toward the end of the log.  Any ideas?
> Is there another way to determine if the patch is successfully installed?
>
> Rob
>
> #-----------------------------------------------------------
> # Vivado v2018.3_AR71898 (64-bit)
> # SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
> # IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
> # Start of session at: Thu Jan 30 11:51:43 2020
> # Process ID: 6739
> # Current directory: /afs/
> crc.nd.edu/user/r/rkossler/uhd/UHD-3.15.0.0/uhd/fpga-src/usrp3/top/n3xx/build-N310_RFNOC_XG
> # Command line: vivado -mode batch -source /afs/
> crc.nd.edu/user/r/rkossler/uhd/UHD-3.15.0.0/uhd/fpga-src/usrp3/top/n3xx/build_n3xx.tcl
> -log build.log -journal n3xx.jou
> # Log file: /afs/
> crc.nd.edu/user/r/rkossler/uhd/UHD-3.15.0.0/uhd/fpga-src/usrp3/top/n3xx/build-N310_RFNOC_XG/build.log
> # Journal file: /afs/
> crc.nd.edu/user/r/rkossler/uhd/UHD-3.15.0.0/uhd/fpga-src/usrp3/top/n3xx/build-N310_RFNOC_XG/n3xx.jou
> #-----------------------------------------------------------
> ...
> ...
> ...
> Attempting to get a license for feature 'Implementation' and/or device
> 'xc7z100'
> INFO: [Common 17-349] Got license for feature 'Implementation' and/or
> device 'xc7z100'
> INFO: [Common 17-1540] The version limit for your license is '2019.07' and
> has expired for new software. A version limit expiration means that,
> although you may be able to continue to use the current version of tools or
> IP with this license, you will not be eligible for any updates or new
> releases.
> INFO: [DRC 23-27] Running DRC with 8 threads
> INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
> INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for
> more information.
> Running DRC as a precondition to command place_design
> INFO: [DRC 23-27] Running DRC with 8 threads
> ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank
> 34. For example, the following two ports in this bank have conflicting
> VCCOs:
> ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
> (LVCMOS18, requiring VCCO=1.800)
> WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit
> reached: 20 violations have been found.
> WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1840 rule limit
> reached: 20 violations have been found.
> ...
> ...
> ...
> INFO: [Vivado_Tcl 4-198] DRC finished with 1 Errors, 52 Warnings
> INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for
> more information.
> ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
> INFO: [Common 17-83] Releasing license: Implementation
> 34 Infos, 63 Warnings, 0 Critical Warnings and 2 Errors encountered.
> place_design failed
> place_design: Time (s): cpu = 00:01:07 ; elapsed = 00:00:58 . Memory (MB):
> peak = 9161.891 ; gain = 0.000 ; free physical = 43703 ; free virtual =
> 93417
> ERROR: [Common 17-39] 'place_design' failed due to earlier errors.
>
>     while executing
> "place_design -directive $pla_dir"
>     (procedure "vivado_strategies::implement_design" line 23)
>     invoked from within
> "vivado_strategies::implement_design $n3xx_strategy"
>     (file "/afs/
> crc.nd.edu/user/r/rkossler/uhd/UHD-3.15.0.0/uhd/fpga-src/usrp3/top/n3xx/build_n3xx.tcl"
> line 28)
> INFO: [Common 17-206] Exiting Vivado at Thu Jan 30 12:40:04 2020...
>
>
>>
>>
>> On Mon, Dec 9, 2019 at 2:43 PM Nate Temple via USRP-users <
>> usrp-users at lists.ettus.com> wrote:
>>
>>> Hi Robert,
>>>
>>> So this is a bug related to Vivado, you will need to install this linked
>>> below patch and it should resolve it.
>>>
>>> https://www.xilinx.com/support/answers/71898.html
>>>
>>> Regards,
>>> Nate Temple
>>>
>>> On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple at ettus.com>
>>> wrote:
>>>
>>>> Hi Robert,
>>>>
>>>> Thanks for the bug report.
>>>>
>>>> If you're just trying to use RFNoC at this point, I would recommend to
>>>> stick with the latest stable release, which at this time is v3.14.1.1.
>>>>
>>>> Note, 3.14.x.x UHD will require Vivado 2017.4.
>>>>
>>>>
>>>> Regards,
>>>> Nate Temple
>>>>
>>>> On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
>>>> usrp-users at lists.ettus.com> wrote:
>>>>
>>>>> Hi all!
>>>>>
>>>>> I tried to compile the default RFNoC image for the N310, using UHD on
>>>>> tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
>>>>>
>>>>> Running "make N310_RFNOC_XG", the IP cores are compiled successfully,
>>>>> but then Vivado shows the following errors:
>>>>>
>>>>> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
>>>>> 'STR_SINK_FIFOSIZE'
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>>>>> ERROR: [Synth 8-521] parameter assignment could not be resolved to a
>>>>> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>>>>> ERROR: [Synth 8-196] conditional expression could not be resolved to a
>>>>> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
>>>>> WARNING: [Synth 8-693] zero replication count - replication ignored
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
>>>>> WARNING: [Synth 8-693] zero replication count - replication ignored
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
>>>>> WARNING: [Synth 8-693] zero replication count - replication ignored
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
>>>>> ERROR: [Synth 8-6156] failed synthesizing module
>>>>> 'noc_shell__parameterized9'
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
>>>>> ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
>>>>> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
>>>>> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
>>>>> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
>>>>>
>>>>> The full build.log file is attached. I did not modify any files, just
>>>>> trying to compile the RFNoC example as provided.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> Btw I also tried to build the default image with "make N310_XG", this
>>>>> one compiles but failed later during DRC:
>>>>>
>>>>> [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank
>>>>> 34. For example, the following two ports in this bank have conflicting
>>>>> VCCOs:
>>>>> ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
>>>>> (LVCMOS18, requiring VCCO=1.800)
>>>>> [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> USRP-users mailing list
>>>>> USRP-users at lists.ettus.com
>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>>>
>>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>
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