[USRP-users] Building RFNoC Image with OOT Module on X310 - Module not found

Felix Greiwe felix.greiwe at tu-dortmund.de
Thu Jan 9 05:49:10 EST 2020


Hi Brian,

thank you for the answer, with your help I was able to successfully build
an Image! One last question: Do I need to worry about all those critical
warnings that popped up during the build? Seems like a lot to me.

Example:

CRITICAL WARNING: [Vivado 12-1790] Evaluation License Warning: This design
contains one or more evaluation cores that will cease to function after a
certain period of time. This design should NOT be used in production
systems.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.
CRITICAL WARNING: [Timing 38-469] The REFCLK pin of IDELAYCTRL
u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/u_idelayctrl_200 has a clock
period of 4.998 ns (frequency 200.080 Mhz) but IDELAYE2
u_ddr3_32bit/u_ddr3_32bit_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2
has REFCLK_FREQUENCY of 200.000 Mhz (period 5.000 ns). The IDELAYCTRL
REFCLK pin frequency must match the IDELAYE2 REFCLK_FREQUENCY property.










Thank you and best regards, Felix

> On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users <
> usrp-users at lists.ettus.com> wrote:
>
>> Hi EJ,
>>
>> thank you for your answer! To make my error more traceable, I created a
>> new OOT Module and added the default gain block from rfnoc getting
>> started.
>>
>> I also took your advice and looked at the uhd_image_builder.py script. I
>> noticed very strange behaviour, because my print statements suggested,
>> that the script did not include my makefile.srcs because it first edited
>> the path
>>
>> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ to
>> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc and a bit later to
>> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/rfnoc/rfnoc/fpga-src/ .
>>
>> As you can see two rfnoc's here hence it did not find the makefile.src
>> in
>> ..../fpga-src. The changes (marked with fgr) in the create_oot_include
>> here seem to resolve the issue, hopefully helpful for other people too
>> and
>> maybe even a major bug?:
>>
>> def create_oot_include(device, include_dirs):
>>     """
>>     Create the include file for OOT RFNoC sources
>>     """
>>     oot_dir_list = []
>>     target_dir = device_dict(device.lower())
>>     dest_srcs_file = os.path.join(get_scriptpath(), '..', '..', 'top',\
>>             target_dir, 'Makefile.OOT.inc')
>>     incfile = open(dest_srcs_file, 'w')
>>     incfile.write(OOT_SRCS_FILE_HDR)
>>     if include_dirs is not None:
>>         for dirs in include_dirs:
>>             currpath = os.path.abspath(str(dirs))
>>             if os.path.isdir(currpath) & (os.path.basename(currpath) ==
>> "rfnoc"):
>>                 # Case 1: Pointed directly to rfnoc directory
>>                 oot_path = currpath
>>             elif os.path.isdir(os.path.join(currpath, 'rfnoc')):
>>                 # Case 2: Pointed to top level rfnoc module directory
>>                 oot_path = os.path.join(currpath, 'rfnoc')
>>             elif os.path.isfile(os.path.join(currpath, 'Makefile.inc')):
>>                 # Case 3: Pointed to a random directory with a
>> Makefile.inc
>>                 oot_path = currpath
>>             else:
>>                 print('No RFNoC module found at ' +
>> os.path.abspath(currpath))
>>                 continue
>>             if oot_path not in oot_dir_list:
>>                 oot_dir_list.append(oot_path)
>>                 named_path = os.path.join('$(BASE_DIR)',
>> get_relative_path(get_basedir(), oot_path))
>>                 incfile.write(OOT_DIR_TMPL.format(oot_dir=named_path))
>>                 if os.path.isfile(os.path.join(oot_path,
>> 'Makefile.inc')):
>>                     # Check for Makefile.inc
>>                     incfile.write(OOT_INC_TMPL)
>>                 elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
>> 'Makefile.inc')):
>>                     # Check for Makefile.inc
>>                     incfile.write(OOT_INC_TMPL)
>>                 #elif os.path.isfile(os.path.join(oot_path, 'rfnoc',
>> 'fpga-src', 'Makefile.srcs')): # Original
>>                 elif os.path.isfile(os.path.join(oot_path, 'fpga-src',
>> 'Makefile.srcs')): # Anders fgr
>>                     # Legacy: Check for fpga-src/Makefile.srcs
>>                     # Read, then append to file
>>                     # curr_srcs = open(os.path.join(oot_path, 'rfnoc',
>> 'fpga-src', 'Makefile.srcs'), 'r').read() # Original
>>                     curr_srcs = open(os.path.join(oot_path, 'fpga-src',
>> 'Makefile.srcs'), 'r').read() # Anders fgr
>>                     # curr_srcs = curr_srcs.replace('SOURCES_PATH',
>> os.path.join(oot_path, 'rfnoc', 'fpga-src', '')) #
>> Original
>>                     curr_srcs = curr_srcs.replace('SOURCES_PATH',
>> os.path.join(oot_path, 'fpga-src', '')) # Anders fgr
>>                     print('Searching for Makefile.srcs: ' + curr_srcs)
>> #fgr
>>                     incfile.write(OOT_SRCS_TMPL.format(sources=curr_srcs))
>>                 else:
>>                     print('No valid makefile found at ' +
>> os.path.abspath(currpath))
>>                     continue
>>
>> However 30 minutes later in the build I got the next errror and again
>> have
>> no idea what to do. My command was:
>>
>> ./uhd_image_builder.py gain ddc fft -I
>> /home/lskt/rfnoc/src/rfnoc-blocks_lskt/ -d x310 -t X310_RFNOC_HG -m 6
>> --fill-with-fifos
>>
>> Using Vivado 2018.3 and UHD 3.15.0.0-124-geb448043
>>
>>
>> Erros are:
>>
>> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4
>> has multiple drivers: radio_clk_gen/inst/clkout1_buf/O, and
>> bus_clk_gen/inst/clkout4_buf/O.
>> ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
>> radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9
>> has
>> multiple drivers:
>>
>> ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
>> and
>>
>> radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
>> ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
>> ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
>> [00:24:46] Current task: DRC +++ Current Phase: Starting
>> [00:24:46] Current task: DRC +++ Current Phase: Finished
>> [00:24:46] Process terminated. Status: Failure
>>
>> ========================================================
>> Warnings:           1304
>> Critical Warnings:  40
>> Errors:             4
>>
>> Makefile.x300.inc:106: recipe for target 'bin' failed
>> make[1]: *** [bin] Error 1
>> make[1]: Verzeichnis ?/home/lskt/rfnoc/src/uhd-fpga/usrp3/top/x300? wird
>> verlassen
>> Makefile:112: recipe for target 'X310_RFNOC_HG' failed
>> make: *** [X310_RFNOC_HG] Error 2
>>
>>
>> Again, I would be very thankful for any advice, I refuse to give up :D
>>
>
> This was recently shown to be a reassignment of the ce_clk and ce_rst
> signals.  In your rfnoc_ce_auto_inst generated file, remove the lines that
> say:
>
>   wire ce_clk = radio_clk;
>   wire ce_rst = radio_rst;
>
> Then try to rebuild.
>
> You can remove those lines from being regenerated every time here:
>
>
> https://github.com/EttusResearch/fpga/blob/fde2a94eb7231af859653db8caaf777ae2b66199/usrp3/tools/scripts/uhd_image_builder.py#L44
>
> Brian
>





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