[USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
C.E.V.Diouf at tudelft.nl
Fri Jan 3 13:41:33 EST 2020
I have this version UHD 3.15.0.git-84-g164d76dc
but the lines are there whenever you use the ./uhd_image_builder.py scripts.
From: Brian Padalino <bpadalino at gmail.com>
Sent: Friday, January 3, 2020 7:25:00 PM
To: Cherif Diouf
Cc: usrp-users at lists.ettus.com
Subject: Re: [USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users <usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>> wrote:
Some hints, for info, I am working with the X310 device, but you can take the big picture.
I previously met such issues, those were related to signal re-definitions.
The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the ce_clk/ce_rst signals by assigning to them radio_clk/radio_rst signals. The issue here is that ce_clk is a clock of its own and is already defined in the top block file *x300.v* at lines 259 and 290. My filepath is rfnoc/src/uhd-fpga/usrp3/top/x300/.
In the 184.108.40.206 code on github I don't see what you're talking about:
Looking at the history of the file, it looked like that might have been removed way back in 2016 in commit c98bc14fe0ea2c27a5629a24d47915eb7e0b6700.
Jerrid - do you have those lines that Cherif is describing?
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