[USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers

Brian Padalino bpadalino at gmail.com
Fri Jan 3 13:25:00 EST 2020


On Fri, Jan 3, 2020 at 1:14 PM Cherif Diouf via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hi Jerrid,
>
>
>
> Some hints, for info,  I am working with the X310 device, but you can
> take the big picture.
>
>
> I previously met  such issues, those were related to signal re-definitions.
>
>
> The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the
> ce_clk/ce_rst signals by assigning to them  radio_clk/radio_rst signals.
> The issue here is that ce_clk is a clock of its own and is already defined
> in the top block file *x300.v* at lines 259 and 290. My filepath is
> rfnoc/src/uhd-fpga/usrp3/top/x300/.
>

In the 3.15.0.0 code on github I don't see what you're talking about:


https://github.com/EttusResearch/fpga/blob/fde2a94eb7231af859653db8caaf777ae2b66199/usrp3/top/x300/rfnoc_ce_auto_inst_x300.v

Looking at the history of the file, it looked like that might have been
removed way back in 2016 in commit c98bc14fe0ea2c27a5629a24d47915eb7e0b6700.

Jerrid - do you have those lines that Cherif is describing?

Brian
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