[USRP-users] Building RFNoC image with default blocks fails, [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers
C.E.V.Diouf at tudelft.nl
Fri Jan 3 13:13:26 EST 2020
Some hints, for info, I am working with the X310 device, but you can take the big picture.
I previously met such issues, those were related to signal re-definitions.
The file *rfnoc_ce_auto_inst_x310.v* at lines 19/20 is re-defining the ce_clk/ce_rst signals by assigning to them radio_clk/radio_rst signals. The issue here is that ce_clk is a clock of its own and is already defined in the top block file *x300.v* at lines 259 and 290. My filepath is rfnoc/src/uhd-fpga/usrp3/top/x300/.
Vivado 2017.4 would just let this pass but when I moved to Vivado 2018.4 the build would each time fail, popping Net having multiple drivers errors.
Changing the ce_clk/ce_rst signals names in the *rfnoc_ce_auto_inst_x310.v* and modifying this instantiation file accordingly will make the build work. The solution is ok If you are using a different custom instantiation file,.
However, I am not sure that in your case it will help, because your *rfnoc_ce_auto_inst_x310.v* file is re-created at each build command. So likely anything you update in the file will be dumped at the next build.
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the USRP-users