[USRP-users] Adding my custom RX module inside the FPGA (USRP b205mini)

Marcus Müller marcus.mueller at ettus.com
Thu Jan 2 19:02:28 EST 2020

Hi Varban,

On Tue, 2019-12-31 at 21:27 +0200, Varban Metodiev wrote:
> Hi Marcus,
> I am doing something like a PWM over radio. I need to measure the
> length of the pulse that is being received. My Verilog module does
> this and outputs a 16-bit variable that stores the samples count
> present in my PWM pulse.

That's a bit unusual, but cool :) This is a curious community, so if
you have any references to the system and its motivations, I think
there might be interest :)

As a development hint: do implement
equivalent functionality for an unmodified USRP on your PC first, so
that you have a "known good" implementation to test against!

> you can either get the DDC output 
> ---> That would be great (and enough at this point). May you please
> help me where to attach my inputs and outputs (see the attached block
> diagram - inputs width will be changed to 32 ot 64bit, of course).

So, you'd usually find `ddc_chain` in radio_legacy.v:

ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24),
     (.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
      .debug(debug_ddc_chain) );

See that `sample` output that is put into `sample_rx`, and the
`strobe_rx`? Those are the signals you're looking for!

You can simply add your module to radio_legacy.v and connect it to
these two signals.

Now, you can try to hook the output of your module to new_rx_framer
(which normally "consumes" sample_rx), but be aware that that framer is
meant for continuous operation as long as flow control tells it. So,
maybe for the beginning, you'd want to design your module to be
*synchronous*, e.g. by emitting "0" in the sample clock until actual
data is available.

> Additionally, how can I expose the register read/write over custom
> UHD modification?

In radio_legacy.v, there's a section called 'user_settings', that comes
with example code :)

> what's the specific motivation to do things on the FPGA?
> ---> At some point I would try to test my PWM approach at 50Msps
> rates. 

Hm, I'm surprised that should work within the maximum sampling rate of
61.44 MS/s of the ADC, and it still sounds like it'd be sensible to do
it in software (a simple state machine, after all), but I see where
you're coming from!

Best regards,
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