[USRP-users] E310 RFNoC image
Joern.Skorstad at Nkom.no
Thu Nov 21 07:23:19 EST 2019
I have successfully built an RFNoC image with a DDC, Window and FFT block using the recipe mentioned. Also I have been able to connect the blocks using the UHD library in a C++ program, and I am receiving FFT output to my program. However, I am still only able to achieve an FFT size of max. 512 bins. Reading an older post it seems this is caused by some FPGA - host packet limit of 4000 bytes?
Anyone been able to achieve more than 512 bins FFT on an E310? I only need the magnitude data of the FFT, and from what I can see the SC16 format is also used when transferring magnitude, which means the imaginery part is not used.
Is it possible to modify the FFT block to do a 1024 bin FFT, and send FFT magnitude data on both real and imag bytes? I tried to look at the code, but no luck... Eventually, is it possible to split the data transfer into several blocks?
Fra: Skorstad,Jørn <Joern.Skorstad at Nkom.no>
Sendt: tirsdag 12. november 2019 18:24
Til: Nate Temple <nate.temple at ettus.com>
Kopi: USRP-users at lists.ettus.com
Emne: Re: [USRP-users] E310 RFNoC image
Thanks Nate, I will try to install it as described below.
12. nov. 2019 17:55 skrev Nate Temple <nate.temple at ettus.com<mailto:nate.temple at ettus.com>>:
The process for installing Xilinx Vivado WebPACK is fairly easy.
Download "Vivado Design Suite - HLx Editions - 2017.4 Full Product Installation" from here:
Decompress the tarball
Run "sudo ./xsetup"
When prompted to download the latest version, ignore and click "Continue", 2017.4 is required.
Click Next, and agree to the EULA and other terms, click Next and keep the default /opt/Xilinx install prefix.
Click next through the rest of the menus and "install"
You'll now have Vivado installed to /opt/Xilinx/Vivado/2017.4 and can use it with the build tools as described in the previously linked app note.
On Mon, Nov 11, 2019 at 11:56 PM Skorstad,Jørn via USRP-users <usrp-users at lists.ettus.com<mailto:usrp-users at lists.ettus.com>> wrote:
I have followed the application note https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source to set up a cross compile environment for an E310 SDR. It works well, however I have not been able to get past chapter 7: Building a custom RFNoC FPGA Image, as I haven't set up Vivado 2017.4, as required.
I would like to experiment with RFNoC development also. The application note states «A future application note will cover a step-by-step install guide for Vivado». Until this application note is ready, is it possible to use an image built by someone else using this software version? (UHD_3.14.1.HEAD-0-gbfb9c1c7). If so, where could I eventually download it? What I need is 1xwindow, 1xFFT, 1xFIFO and 1xFosphor if there is space left. Radio and DDC is already on FPGA available as blocks?
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