[USRP-users] Issues with RFNoC Component Test Bench

Jonathan Lockhart jlockhartrt at gmail.com
Wed Nov 13 10:53:14 EST 2019


Greetings USRP Users,

I am having another issue with the UHD-3.14 build I can't seem to shake
down. I have been going through this guide on the KB to learn how to use
the rfnocmodtool to build new modules for my E312:

https://kb.ettus.com/Getting_Started_with_RFNoC_Development

Unfortunately, when I get to the point of using the test bench, I get the
following error.

ettus_sdr at ettus-VirtualBox:~/rfnoc/src/rfnoc-tutorial/build$ sudo make
noc_block_gain_tb
[sudo] password for ettus_sdr:
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)

Environment successfully initialized.
BUILDER: Checking tools...
* GNU bash, version 4.4.20(1)-release (x86_64-pc-linux-gnu)
* Python 2.7.15+
* Vivado v2017.4.1 (64-bit)

****** Vivado v2017.4.1 (64-bit)
  **** SW Build 2117270 on Tue Jan 30 15:31:13 MST 2018
  **** IP Build 2095745 on Tue Jan 30 17:13:15 MST 2018
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source
/home/ettus_sdr/rfnoc/src/uhd/fpga-src/usrp3/tools/scripts/viv_sim_project.tcl
# set simulator       $::env(VIV_SIMULATOR)
# set design_srcs     $::env(VIV_DESIGN_SRCS)
# set sim_srcs        $::env(VIV_SIM_SRCS)
# set inc_srcs        $::env(VIV_INC_SRCS)
# set sim_top         $::env(VIV_SIM_TOP)
# set part_name       $::env(VIV_PART_NAME)
# set sim_runtime     $::env(VIV_SIM_RUNTIME)
# set sim_fast        $::env(VIV_SIM_FAST)
# set vivado_mode     $::env(VIV_MODE)
# set working_dir     [pwd]
# set sim_fileset "sim_1"
# set project_name "[string tolower $simulator]_proj"
# if [info exists ::env(VIV_SIM_COMPLIBDIR) ] {
#     set sim_complibdir  $::env(VIV_SIM_COMPLIBDIR)
#     if [expr [file isdirectory $sim_complibdir] == 0] {
#         set sim_complibdir  ""
#     }
# } else {
#     set sim_complibdir  ""
# }
# if [expr ([string equal $simulator "XSim"] == 0) && ([string length
$sim_complibdir] == 0)] {
#     puts "BUILDER: \[ERROR\]: Could not resolve the location for the
compiled simulation libraries."
#     puts "                  Please build libraries for chosen simulator
and set the env or"
#     puts "                  makefile variable SIM_COMPLIBDIR to point to
the location."
#     exit 1
# }
# puts "BUILDER: Creating Vivado simulation project part $part_name"
BUILDER: Creating Vivado simulation project part xc7k410tffg900-2
# create_project -part $part_name -force $project_name/$project_name
WARNING: [Device 21-436] No parts matched 'xc7k410tffg900-2'
ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Wed Nov 13 10:44:55 2019...
/home/ettus_sdr/rfnoc/src/uhd/fpga-src/usrp3/top/../tools/make/viv_simulator.mak:51:
recipe for target 'xsim' failed
make[4]: *** [xsim] Error 1
CMakeFiles/noc_block_gain_tb.dir/build.make:57: recipe for target
'CMakeFiles/noc_block_gain_tb' failed
make[3]: *** [CMakeFiles/noc_block_gain_tb] Error 2
CMakeFiles/Makefile2:131: recipe for target
'CMakeFiles/noc_block_gain_tb.dir/all' failed
make[2]: *** [CMakeFiles/noc_block_gain_tb.dir/all] Error 2
CMakeFiles/Makefile2:138: recipe for target
'CMakeFiles/noc_block_gain_tb.dir/rule' failed
make[1]: *** [CMakeFiles/noc_block_gain_tb.dir/rule] Error 2
Makefile:201: recipe for target 'noc_block_gain_tb' failed
make: *** [noc_block_gain_tb] Error 2

The tutorial has you build a gain module, and I have verified the code is
copied as they provide it in the guide, with no other extras provided by
the build script being modified.

I also verified that the cmake for the test bench was provided the correct
FPGA source repository and it picked it up in the build phase.

Regards,
Jon
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