[USRP-users] Phase drift issue of N310

Ali Dormiani sdormian at eng.ucsd.edu
Thu Mar 14 17:07:21 EDT 2019


Hello all,

Sorry for spreading misinformation. I frequently conflate clock and LO
incorrectly. Additionally the results I posted are for an array of multiple
N310's which definitely have different clocks.

I was taught in class that carrier frequency offset happens when an access
point (AP) and client have imperfect LO's. (EX. wifi router at 2.41 GHz and
laptop at 2.39 Ghz).

Looking at the block diagram, could separate LO's for each AD9361 be the
source of this phase behavior?






On Thu, Mar 14, 2019 at 1:39 PM Damon via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hi Marcus,
>
> The UHD Version is v3.14.0.0-rc1.
>
> Best regards,
>
> Damon
>
> >> Hi Ali,
> >>
> >> The daughterboards have their own clock generators, but they are not
> >> exactly 'independent'. At least they don't have to be, as they share the
> >> same reference clock. Look at the block diagram:
> >>
> >> https://kb.ettus.com/images/9/9d/USRP_N310_N300_DB_Schematic.pdf
> >>
> >> and "Ref Clock" block. I don't have N310 and I know that reality can be
> >> a bit far from expectations (i.e. look at my "What makes sense and what
> >> doesn't in the way carrier frequency is set for TwinRX currently?"
> post).
> >>
> >> But maybe the daughterboards can be configured to use that reference
> clock.
> >>
> >>
> >> Best Regards,
> >> Piotr Krysik
> > The LMK clock generator uses the reference clock from the mainboard, so
> > there should not be any mutual phase-jitter/drift issues.  I can test
> this
> >     on my N310 in the coming day or two.
> >
> > What version of UHD is in use?
>
>
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