[USRP-users] Frequency resolution of UBX-160 with integer N mode

Marcus Müller marcus.mueller at ettus.com
Thu Mar 7 04:50:15 EST 2019


Good description!
If you look into uhd/host/lib/usrp/dboard/dboard_ubx.cpp (I think), you
should find that the constructor looks through all the rates the
motherboard (X310 in your case) has to offer and picks the highest one
that works with your UBX. That'd be 25 MHz for the 0. revision of the
UBX, and 50 MHz for any after that (which you extremely likely have).

Best regards,
Marcus
On Thu, 2019-03-07 at 10:14 +0100, Andreas Leuenberger via USRP-users
wrote:
> Hi Fabian
> 
> Thank you for your answer.
> I have check the schematics of the X310. The reference clocks to the 
> daughter boards and the 200 MHz sampling clocks are both generated 
> by the "clock jitter clean" chip (LMK0481). I did not have time yet
> to
> check the configuration of this chip, but probably you are right and
> the reference clock to the daughter boards is not 10 MHz (as I
> assumed).
> It could be 200 MHz or directly 50 MHz.
> 
> Best regards,
> andreas
> 
> 
> > Hi,
> >
> > please double check on that, as I am not 100% sure.
> > As far as I was able to figure out, the LO is generated from the 
> > Daughterboard internal 200 MHz reference (which is dirived from the
> 10 
> > MHz), but is divided by 4 for some reason, so you get multiples of
> 50 
> > MHz. This will also induce a random 90° phase shift between the
> signals, 
> > which is a big problem for MIMO stuff.
> > At least the TwinRX boards we used were able to share the LO
> between 
> > multiple channels, which fixed the problem for us.
> >
> > Best regards,
> > Fabian
> >
> > Am 04.03.2019 um 17:23 schrieb Andreas Leuenberger via USRP-users:
> > > Hello all,
> > > 
> > > I am using a USRP X310 with two daughter boards UBX-160 v2. To
> get a 
> > > stable phase difference of the two daughter boards, I use the RX
> LOs in 
> > > integer N mode ("mode_n=integer"). - I have noticed that the
> frequency 
> > > step of the LO is 50 MHz. As the frequency of the reference
> signal is 10 
> > > MHz, I would expect a step of 10 MHz.
> > > 
> > > Is there a way to reduce this frequency step?
> > > 
> > > Thanks for your help,
> > > andreas
> > > 
> > > 
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> > > USRP-users at lists.ettus.com
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> 
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