[USRP-users] different phase difference using splitter on each run

Marcus D. Leech patchvonbraun at gmail.com
Tue Mar 5 22:52:22 EST 2019


On 03/05/2019 10:41 PM, Koyel Das (Vehere) wrote:
>
> The timed commands are as follows in rx_multisamples.cpp
>
>
> if(sync=="now"){
>
> 	//This is not a true time lock, the devices will be off by a few RTT.
>
> 	//Rather, this is just to allow for demonstration of the code below.
>
> 	usrp->set_time_now(uhd::time_spec_t(0.0));
>
> 	}
>
> 	else if (sync == "pps"){
>
> 	usrp->set_time_source("external");
>
> 	usrp->set_time_unknown_pps(uhd::time_spec_t(0.0));
>
> 	boost::this_thread::sleep(boost::posix_time::seconds(1)); //wait for 
> pps sync pulse
>
> 	}
>
> 	else if (sync == "mimo"){
>
> 	UHD_ASSERT_THROW(usrp->get_num_mboards() == 2);
>
> 	
>
> 	//make mboard 1 a slave over the MIMO Cable
>
> 	usrp->set_clock_source("mimo", 1);
>
> 	usrp->set_time_source("mimo", 1);
>
> 	
>
> 	//set time on the master (mboard 0)
>
> 	usrp->set_time_now(uhd::time_spec_t(0.0), 0);
>
> 	
>
> 	//sleep a bit while the slave locks its time to the master
>
> 	boost::this_thread::sleep(boost::posix_time::milliseconds(100));
>
> 	}
>
> 1. "now", 2 ."pps" and 3. "mimo"
>
> I was using "now" but still I don't get same phase difference in each 
> run. Is there any other time command that I have to use or what do I 
> have to set?
>
> Regards,
Ah!  You have a misunderstanding about what I mean by "timed commands".

See the "test_timed_commands" example in the source code tree.

See also the documentation here:

https://files.ettus.com/manual/page_sync.html

Basically, you need to make sure that all the devices agree on what time 
it is (if you have only one device, this is "easy").  Once you have that,
   THEN, you need to make sure that all the RF synthesizer tuning 
happens at precisely the same instant, so that the re-synch feature
   (if the device has one) can be triggered at exactly the same time.

Without that, the synthesizers are free to "lock" at any phase-angle 
with respect to the reference clock, and further the reference
   divider in a synthesizer is guaranteed to be in the same state across 
all synthesizers, even when they're using the same
   reference clock.  This is what the "resynch" hardware signal is all 
about, and what the set_command_time()/clear_command_time()
   API is all about.




-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20190305/53770f39/attachment.html>


More information about the USRP-users mailing list