[USRP-users] Hardware clocks, X310

Ian Buckley ianb at ionconcepts.com
Thu Feb 28 11:36:10 EST 2019

1) Changing the radio clock frequency is not simple and would leave you an immense amount of knock on problems to address.
2) ADC and DAC are tightly coupled to the radio clk, they run on low jitter versions of the same clock.
3) Absolutely, and that is the beauty of streaming style packet buses like the AXI4 stream protocol that the X310 is built around. It’s a relatively easy task to cross this type of bus into a different clock domain, do work on the payload, and cross it back. The modular RTL code supplied by Ettus already contains all the functional blocks you would need to do this.

So saying that it’s always a good thing to minimize the number of clock domains in a design as it adds significant overhead and complexity, not to mention a verification burden. Evaluate hard if you really need another frequency, especially when its an integer fraction of a clock that already exists. 200MHz is not a hard frequency to attain in Virtex-7 with well designed logic. 

> On Feb 28, 2019, at 7:05 AM, Cherif Diouf via USRP-users <usrp-users at lists.ettus.com> wrote:
> Hello guys,
> I am a researcher working with the X310 USRP. I have a couple of questions regarding the Hardware clocks.
> The bus_clock and radio_clk are by default respectively set at 166 MHz and 200 MHz.
> And if I am right the crossbar clock ce_clk is also at 200 MHz. Is there a solution to bring it down to ce_clk = 50 MHz, in that case
> 1)      Does it mean that all the Kintex XC410T blocks will run at 50 MHz ? Is this safe?
> 2)       What about the ADC and DAC and their sampling clock?
> 3)      Finally can we have different RFnoc blocks running at different clock frequencies and still have the  crossbar  running at a given clock frequency?
> Best Regards
> Cherif
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