[USRP-users] E310 RFNoC FFT Overrun Issue

Jonathon Pendlum jonathon.pendlum at ettus.com
Mon Feb 11 00:09:43 EST 2019

Hi Ramazan,

I would suggest first testing with a signal generated with GNU Radio. For
example, use a Fast Noise Source + Low Pass Filter to crudely simulate
receiving a wide band signal. See what it looks like without running it
through RFNoC. Then replace the RFNoC radio block with those blocks and
look at the result.

You should also consider using the ZeroMQ blocks to forward data over
Ethernet to a host PC to view your data in real time. Look at the gr-ettus
example flowgraphs rfnoc_fft_network_usrp (runs on E310) and
rfnoc_fft_network_host (runs on host PC).

One guess I can make is try increasing the FFT RFNoC block gain. By
default, it is set to a very conservative value, so try changing it to 21.
That gain value sets the Xilinx's FFT IP core scaling schedule, which you
can read about here:
(see SCALE_SCH on page 15, the core uses Radix-4). You can also try
adjusting it with a slider in real time. Note that it may behave a bit odd
as it is not a linear mapping due to the scaling schedule format.

The overflows are due to either the ARM processors cannot keep up with the
processing load or the SD card write speed is too slow. Try increasing N in
Keep One in N.


On Mon, Feb 11, 2019 at 5:51 AM Ramazan Çetin <ramazan.cetin at gohm.com.tr>

> Hi Jonathon,
> I fixed the RFNOC: Vector IIR issue with changing its coefficients. Now i
> can get samples using Vector IIR and keep 1 in N. I just tried to get Wifi
> samples using this;
> RFNOC: radio(56Mhz) -> RFNOC: FFT -> RFNOC: Vector_iir -> RFNOC: keep 1 in
> N(N = 14) -> FileSink
> I am receiving samples from CPU as 4M. But i am sampling signal with 56Mhz
> and decimate it after FFT. So, i should get 56Mhz bandwidth signal. But
> when i look my signal on CPU, it looks small bandwidth. Wifi is 20 or 40MHz
> bandwidth so i should see some gap on frequency axis, but i cannot. I have
> attached my flowgraph and wifi spectrogram.
> Q1. Is it related with keep 1 in N? Is it keeping first N samples from FFT
> bins? or i am missing something else. Is it possible to see 56 MHz
> bandwidth signal on host?
> Q2. I am getting "Ooverrun on chan 0" after 3 or 4 seconds. Is it CPU's
> capacity for processing? After some time it cannot catch that speed. Maybe
> i need some FIFO. Is it right?
> Thank you so much for your answers. Best regards.
> Ramazan
> On 10.02.2019 15:54, Ramazan Çetin wrote:
> Hi Jonathon,
> Thank you for your reply. I just tried what you said and investigated
> gr-ettus/examples/rfnoc/rfnoc_vector_iir.grc. I firstly tried without using
> keep 1 in N block. I just sampled 2MHz and try to get FM radio samples of
> spectrum. My flowgraph is attached.
> My problem is when i used RFNOC: radio -> RFNOC: FFT -> VecToStr ->
> IIR_filter(not RFNOC) -> StrToVect -> CompToMag -> Log10 -> FileSink
> with same coefficients it is working good. I can get spectrum samples.
> But when i use RFNOC: radio -> RFNOC: FFT -> RFNOC: Vector_iir ->
> CompToMag -> Log10 -> FileSink
> it gives all zeros after its output. Coefficients are same. I just changed
> IIR filter with RFNOC Vector IIR. Do you know why it is happening?
> Best regards.
> On 10.02.2019 10:21, Jonathon Pendlum wrote:
> Hi Ramazan,
> Q1. So, do you know any method to minimize signal distortion while
>> downsampling in frequency domain? or How can i get wifi signal frequency
>> spectrum in E310 ?
> You want to filter the vector of FFT bins individually, which is not what
> the DDC block is designed to do. Instead, you should use the VectorIIR and
> Keep 1 in N RFNoC blocks in this configuration: RFNoC Radio -> RFNoC FFT ->
> RFNoC VectorIIR -> RFNoC Keep 1 in N -> Host. For an example, look at the
> gr-ettus flowgraph in gr-ettus/examples/rfnoc/rfnoc_vector_iir.grc.
>> Q2. When i try compiling FPGA image with 4 blocks, it gives "Placer
>> could not place all instances" error. But in guide, it says user can put
>> up to 6 blocks. Why it give that error after 3 blocks?
> The FPGA fabric has a finite amount of resources (LUTs, Registers, BRAMs,
> DSP48s) and your configuration required more resources than available. The
> 6 block limit is more of a rule of thumb, especially when using small
> blocks like the RFNoC FIFO blocks. You can certainly use up all the FPGA
> resources with less than 6 RFNoC blocks. In your case, a build with just
> the FFT, VectorIIR, and Keep One in N RFNoC blocks should fit.
> Jonathon
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