[USRP-users] E310 RFNoC FFT Overrun Issue
jonathon.pendlum at ettus.com
Sun Feb 10 02:21:39 EST 2019
Q1. So, do you know any method to minimize signal distortion while
> downsampling in frequency domain? or How can i get wifi signal frequency
> spectrum in E310 ?
You want to filter the vector of FFT bins individually, which is not what
the DDC block is designed to do. Instead, you should use the VectorIIR and
Keep 1 in N RFNoC blocks in this configuration: RFNoC Radio -> RFNoC FFT ->
RFNoC VectorIIR -> RFNoC Keep 1 in N -> Host. For an example, look at the
gr-ettus flowgraph in gr-ettus/examples/rfnoc/rfnoc_vector_iir.grc.
> Q2. When i try compiling FPGA image with 4 blocks, it gives "Placer
> could not place all instances" error. But in guide, it says user can put
> up to 6 blocks. Why it give that error after 3 blocks?
The FPGA fabric has a finite amount of resources (LUTs, Registers, BRAMs,
DSP48s) and your configuration required more resources than available. The
6 block limit is more of a rule of thumb, especially when using small
blocks like the RFNoC FIFO blocks. You can certainly use up all the FPGA
resources with less than 6 RFNoC blocks. In your case, a build with just
the FFT, VectorIIR, and Keep One in N RFNoC blocks should fit.
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the USRP-users