[USRP-users] E310 RFNoC FFT Overrun Issue

Ramazan Çetin ramazan.cetin at gohm.com.tr
Sat Feb 9 07:05:48 EST 2019


Hello all,

I want to get fft of 50Ms/s signal and after fft using DDC i will pass 
the samples with 1-5Ms/s to ARM processor.

I have compiled an FPGA image with FFT, DDC and FIFO.

|   |     _____________________________________________________
|   |    /
|   |   |       RFNoC blocks on this device:
|   |   |
|   |   |   * Radio_0
|   |   |   * DDC_0
|   |   |   * FFT_0
|   |   |   * FIFO_0

I have a gnuradio flowgraph (It is attached);

Radio -> strToVector -> FIFO -> FFT -> vectorToStr -> CompToMag -> NullSink

When i used master clock rate 1M, there is no overruns. After 1M for 
example (1.5M) i am getting overruns.

[INFO] [E300] Performing register loopback test...
[INFO] [E300] Register loopback test passed
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000000)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000)
[WARNING] [RFNOC] Can't find a block controller for key FFT, using 
default block controller!
[INFO] [0/FFT_0] Initializing block control (NOC ID: 0xFF70000000000000)
[INFO] [0/FIFO_0] Initializing block control (NOC ID: 0xF1F0000000000000)
[WARNING] [RFNOC] Assuming max packet size for 0/FIFO_0
Press Enter to quit: overrun on chan 0O
overrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan 0
Ooverrun on chan O0
overrun on chan 0

So, why is this happening? I thought i am handling data in FPGA so i can 
get FFT of 50Ms/s signal. I just need to reduce sampling rate when i 
pass the samples to ARM processor. What is wrong with my setup?

Thank you. Best regards.

Ramazan

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