[USRP-users] Live rate changes within an RFNOC block

Andrew Danowitz andrew at whitefoxdefense.com
Mon Feb 4 19:29:52 EST 2019


Thanks for the feedback. I've simulated the block and got it working with
no errors over a few million samples as long as I assert axi_rate_change's
clear when I change N (I've been swapping rates once every 200
transmissions in the testbench). I still get the timeout error in hardware,
though. Could clearing be messing up some stored packet header information
that simulation wouldn't catch?

Thanks,
Andrew

On Mon, Jan 28, 2019 at 4:34 PM Jonathon Pendlum <jonathon.pendlum at ettus.com>
wrote:

> Hi Andrew,
>
> Have you simulated or used chipscope on your block? There is an output
> from axi rate change called "error_extra_outputs" that can be useful. Does
> it assert ever assert? If so, that means your user code has output more
> samples than axi rate change was expecting. If any extra samples come out,
> that breaks axi rate change's tracking of the input sample to output sample
> ratio, which can eventually lead to a lock up.
>
> Jonathon
>
> On Tue, Jan 29, 2019 at 3:11 AM Andrew Danowitz via USRP-users <
> usrp-users at lists.ettus.com> wrote:
>
>> I have an RFNOC block that, based on a control register can either
>> decimate the signal it's working on or leave the output rate the same as
>> the input rate. If I set the control register to an initial value (either
>> decimate, or not decimate) and let the system run, it works fine in either
>> mode. If I try to change the decimation mode while the block is running, I
>> start getting timeout errors. I currently use the axi_rate_change block to
>> help handle the rate change, and have tried to synchronize changing the
>> block's mode (decimate or not) with the axi_rate_change's clear_user flag.
>> Any thoughts?
>>
>> Thanks,
>> Andrew
>>
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