[USRP-users] Custom RFNOC fpga image build failed

Ramazan Çetin ramazan.cetin at gohm.com.tr
Mon Feb 4 02:06:46 EST 2019


Hi Jonathon,

I chowned ~/.Xilinx and other folder etc. it did not work. I installed 
Vivado to another directory (/home/rcetin/opt/), it also did not work. I 
got the same error. I am running all these things on virtual machine. 
Maybe problem can be related with it. I also will try in real machine.

Do you know i should make something extra in Vivado 2017.4 Webpack 
licencing (Webpack need no licence file it should directly work) ? And 
can we use Vivado 2018.2 (I have full product licence on this program)?

Best regards.


On 3.02.2019 14:17, Jonathon Pendlum wrote:
> Hi Ramazan,
>
> I would give chowning both your Xilinx install and ~/.Xilinx to your 
> username a try. If that doesn't work, try reinstalling the Xilinx tools.
>
> Jonathon
>
> On Sun, Feb 3, 2019 at 4:49 PM Ramazan Çetin 
> <ramazan.cetin at gohm.com.tr <mailto:ramazan.cetin at gohm.com.tr>> wrote:
>
>     Hi Jonathon,
>
>     Thank you for your answer. I have tried building default X310
>     image and got this error.
>
>     make -f Makefile.x300.inc bin NAME=X310_HG ARCH=kintex7
>     PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1
>     SFP1_10GBE=1  X310=1 TOP_MODULE=x300 EXTRA_DEFS="BUILD_1G=1
>     BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1  X310=1"
>     make[1]: Entering directory
>     '/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/x300'
>     BUILDER: Checking tools...
>     * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
>     * Python 2.7.12
>     * Vivado v2017.4 (64-bit)
>     ========================================================
>     BUILDER: Building IP ten_gig_eth_pcs_pma
>     ========================================================
>     BUILDER: Staging IP in build directory...
>     BUILDER: Reserving IP location:
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma
>     BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2...
>     BUILDER: Building IP...
>     [00:00:00] Executing command: vivado -mode batch -source
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/tools/scripts/viv_generate_ip.tcl
>     -log ten_gig_eth_pcs_pma.log -nojournal
>     [00:00:10] Current task: Initialization +++ Current Phase: Starting
>     WARNING: [Device 21-436] No parts matched 'xc7k410tffg900-2'
>     ERROR: [Coretcl 2-106] Specified part could not be found.
>     [00:00:10] Current task: Initialization +++ Current Phase: Finished
>     [00:00:10] Process terminated. Status: Failure
>
>     ========================================================
>     Warnings:           1
>     Critical Warnings:  0
>     Errors:             1
>
>     BUILDER: Releasing IP location:
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc:41:
>     recipe for target
>     '/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out'
>     failed
>     make[1]: ***
>     [/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out]
>     Error 1
>     make[1]: Leaving directory
>     '/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/x300'
>     Makefile:72: recipe for target 'X310_HG' failed
>     make: *** [X310_HG] Error 2
>
>     I think it can be licence related problem. Because i installed
>     webpack version of Vivado (This version requires no licence)
>
>     When i try building default E310 image;
>
>     cd .../top/e300
>
>     source setupenv.sh
>
>     make E310_sg3
>
>     I got the same error as before.
>
>     make -f Makefile.e300.inc bin NAME=E310_sg3 ARCH=zynq
>     PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 E310=1 E3XX_SG3=1
>     EXTRA_DEFS="E310=1 E3XX_SG3=1"
>     make[1]: Entering directory
>     '/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
>     BUILDER: Checking tools...
>     * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
>     * Python 2.7.12
>     * Vivado v2017.4 (64-bit)
>     ========================================================
>     BUILDER: Building IP axi4_to_axi3_protocol_converter
>     ========================================================
>     BUILDER: Staging IP in build directory...
>     BUILDER: Reserving IP location:
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter
>     BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
>     BUILDER: Building IP...
>     [00:00:00] Executing command: vivado -mode batch -source
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/tools/scripts/viv_generate_ip.tcl
>     -log axi4_to_axi3_protocol_converter.log -nojournal
>     CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>     /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
>     This IP will not be included in the IP Catalog.
>     CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>     /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
>     This IP will not be included in the IP Catalog.
>     WARNING: [IP_Flow 19-4994] Overwriting existing constraint file
>     '/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter_ooc.xdc'
>     CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>     /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
>     This IP will not be included in the IP Catalog.
>     CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>     /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
>     This IP will not be included in the IP Catalog.
>     [00:00:11] Current task: Initialization +++ Current Phase: Starting
>     [00:00:11] Current task: Initialization +++ Current Phase: Finished
>     [00:00:11] Executing Tcl: synth_design -top
>     axi4_to_axi3_protocol_converter -part xc7z020clg484-3 -mode
>     out_of_context
>     [00:00:11] Starting Synthesis Command
>     ERROR: [filemgmt 56-148]
>     @57j-140@/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/xpm_cdc.xml1
>     ERROR: [Common 17-53] User Exception: No open design. Please open
>     an elaborated, synthesized or implemented design before executing
>     this command.
>     ERROR: [Common 17-53] User Exception: No open design. Please open
>     an elaborated, synthesized or implemented design before executing
>     this command.
>     ERROR: [Common 17-53] User Exception: No open design. Please open
>     an elaborated, synthesized or implemented design before executing
>     this command.
>     ERROR: [Common 17-53] User Exception: No open design. Please open
>     an elaborated, synthesized or implemented design before executing
>     this command.
>     ERROR: [Common 17-53] User Exception: No open design. Please open
>     an elaborated, synthesized or implemented design before executing
>     this command.
>     ERROR: [Common 17-53] User Exception: No open design. Please open
>     an elaborated, synthesized or implemented design before executing
>     this command.
>     [00:00:12] Current task: Synthesis +++ Current Phase: Starting
>     ERROR: [Vivado 12-398] No designs are open
>     [00:00:12] Current task: Synthesis +++ Current Phase: Finished
>     [00:00:12] Process terminated. Status: Failure
>
>     ========================================================
>     Warnings:           1
>     Critical Warnings:  4
>     Errors:             8
>
>     BUILDER: Releasing IP location:
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter
>     /home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/ip/axi4_to_axi3_protocol_converter/Makefile.inc:15:
>     recipe for target
>     '/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci'
>     failed
>     make[1]: ***
>     [/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-3/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci]
>     Error 1
>     make[1]: Leaving directory
>     '/home/rcetin/rfnoc/src/uhd/fpga-src/usrp3/top/e300'
>     Makefile:60: recipe for target 'E310_sg3' failed
>     make: *** [E310_sg3] Error 2
>
>     The error says it cannot read ip file.
>
>     CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>     /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
>     This IP will not be included in the IP Catalog.
>
>     I installed Xilinx Vivado using root privileges. Can the problem
>     related with privileges ? I think Webpack version is okay for E310
>     (No licence reuires).
>
>     Thank you for your time.
>
>     Best regards.
>     On 3.02.2019 06:22, Jonathon Pendlum wrote:
>>     Hi Ramazan,
>>
>>     I was able to build an E310 RFNoC image with a DDC and FFT block
>>     from master (e57dfe075) on the FPGA repo, so I don't think there
>>     is an issue with the code base. The error messages make me wonder
>>     if your Vivado install is corrupt. Are you able to build any
>>     other images, such as the default X310 image (i.e. run 'source
>>     setupenv.sh; make X310_HG' in the fpga/usrp3/top/x300 dir)?
>>
>>     Jonathon
>>
>>     On Sun, Feb 3, 2019 at 6:53 AM Ramazan Çetin via USRP-users
>>     <usrp-users at lists.ettus.com <mailto:usrp-users at lists.ettus.com>>
>>     wrote:
>>
>>         Hello all, (Sorry about multiple messages. I guess i had a
>>         problem about
>>         my mail client)
>>
>>         I am trying to build custom FPGA image for E310 which
>>         includes DDC and FFT.
>>
>>         I compiled and installed;
>>
>>         - UHD master branch (using -DENABLE_RFNOC=ON)
>>
>>         - gnuradio v3.7.13.4
>>
>>         - gr-ettus master
>>
>>         After installing i have checked version of UHD.
>>
>>         UHD version: 3.14.0.0-0-gabf0db4e
>>
>>         Then according to instructions in this page :
>>         https://kb.ettus.com/Getting_Started_with_RFNoC_Development
>>
>>         I cloned https://github.com/EttusResearch/fpga.git repo. I
>>         have Xilinx
>>         Vivado 2017.4 webpack.
>>
>>         Then, I setup environment from fpga/usrp3/top/e300/setupenv.sh.
>>
>>         cd {USER_PREFIX}/fpga/usrp3/tools/scripts
>>         ./uhd_image_builder.py ddc fft -d e310 -t E310_RFNOC_sg3 -m 5
>>         --fill-with-fifos
>>
>>         --Using the following blocks to generate image:
>>              * ddc
>>              * fft
>>         Adding CE instantiation file for 'E310_RFNOC_sg3'
>>         changing temporarily working directory to
>>         /home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/../../top/e300
>>         Setting up a 64-bit FPGA build environment for the USRP-E3x0...
>>         - Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
>>
>>         Environment successfully initialized.
>>         make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
>>         PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1
>>         EXTRA_DEFS="RFNOC=1 E310=1"
>>         make[1]: Entering directory
>>         '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
>>         BUILDER: Checking tools...
>>         * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
>>         * Python 2.7.12
>>         * Vivado v2017.4 (64-bit)
>>         ========================================================
>>         BUILDER: Building IP axi_dma_stream
>>         ========================================================
>>         BUILDER: Staging IP in build directory...
>>         BUILDER: Reserving IP location:
>>         /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
>>         BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
>>         BUILDER: Building IP...
>>         [00:00:00] Executing command: vivado -mode batch -source
>>         /home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/viv_generate_ip.tcl
>>         -log
>>         axi_dma_stream.log -nojournal
>>         CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>>         /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
>>
>>         This IP will not be included in the IP Catalog.
>>         CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>>         /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
>>
>>         This IP will not be included in the IP Catalog.
>>         CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>>         /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
>>
>>         This IP will not be included in the IP Catalog.
>>         CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
>>         /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
>>
>>         This IP will not be included in the IP Catalog.
>>         [00:00:13] Current task: Initialization +++ Current Phase:
>>         Starting
>>         [00:00:13] Current task: Initialization +++ Current Phase:
>>         Finished
>>         [00:00:13] Executing Tcl: synth_design -top axi_dma_stream -part
>>         xc7z020clg484-3 -mode out_of_context
>>         [00:00:13] Starting Synthesis Command
>>         [00:00:13] Current task: Synthesis +++ Current Phase: Starting
>>         ERROR: [filemgmt 56-148]
>>         @57j-140@/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/xpm_cdc.xml1
>>         ERROR: [Common 17-53] User Exception: No open design. Please
>>         open an
>>         elaborated, synthesized or implemented design before
>>         executing this command.
>>         ERROR: [Common 17-53] User Exception: No open design. Please
>>         open an
>>         elaborated, synthesized or implemented design before
>>         executing this command.
>>         ERROR: [Common 17-53] User Exception: No open design. Please
>>         open an
>>         elaborated, synthesized or implemented design before
>>         executing this command.
>>         ERROR: [Common 17-53] User Exception: No open design. Please
>>         open an
>>         elaborated, synthesized or implemented design before
>>         executing this command.
>>         ERROR: [Common 17-53] User Exception: No open design. Please
>>         open an
>>         elaborated, synthesized or implemented design before
>>         executing this command.
>>         ERROR: [Common 17-53] User Exception: No open design. Please
>>         open an
>>         elaborated, synthesized or implemented design before
>>         executing this command.
>>         ERROR: [Vivado 12-398] No designs are open
>>         [00:00:14] Current task: Synthesis +++ Current Phase: Finished
>>         [00:00:14] Process terminated. Status: Failure
>>
>>         ========================================================
>>         Warnings:           0
>>         Critical Warnings:  4
>>         Errors:             8
>>
>>         BUILDER: Releasing IP location:
>>         /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
>>         /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/ip/axi_dma_stream/Makefile.inc:15:
>>
>>         recipe for target
>>         '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci'
>>
>>         failed
>>         make[1]: ***
>>         [/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci]
>>
>>         Error 1
>>         make[1]: Leaving directory
>>         '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
>>         Makefile:70: recipe for target 'E310_RFNOC_sg3' failed
>>         make: *** [E310_RFNOC_sg3] Error 2
>>
>>         Can you please point me what i did wrong ?
>>
>>         Best Regards.
>>
>>
>>         _______________________________________________
>>         USRP-users mailing list
>>         USRP-users at lists.ettus.com <mailto:USRP-users at lists.ettus.com>
>>         http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
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