[USRP-users] Custom RFNOC fpga image build failed

Jonathon Pendlum jonathon.pendlum at ettus.com
Sat Feb 2 22:22:51 EST 2019


Hi Ramazan,

I was able to build an E310 RFNoC image with a DDC and FFT block from
master (e57dfe075) on the FPGA repo, so I don't think there is an issue
with the code base. The error messages make me wonder if your Vivado
install is corrupt. Are you able to build any other images, such as the
default X310 image (i.e. run 'source setupenv.sh; make X310_HG' in the
fpga/usrp3/top/x300 dir)?

Jonathon

On Sun, Feb 3, 2019 at 6:53 AM Ramazan Çetin via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hello all, (Sorry about multiple messages. I guess i had a problem about
> my mail client)
>
> I am trying to build custom FPGA image for E310 which includes DDC and FFT.
>
> I compiled and installed;
>
> - UHD master branch (using -DENABLE_RFNOC=ON)
>
> - gnuradio v3.7.13.4
>
> - gr-ettus master
>
> After installing i have checked version of UHD.
>
> UHD version: 3.14.0.0-0-gabf0db4e
>
> Then according to instructions in this page :
> https://kb.ettus.com/Getting_Started_with_RFNoC_Development
>
> I cloned https://github.com/EttusResearch/fpga.git repo. I have Xilinx
> Vivado 2017.4 webpack.
>
> Then, I setup environment from fpga/usrp3/top/e300/setupenv.sh.
>
> cd {USER_PREFIX}/fpga/usrp3/tools/scripts
> ./uhd_image_builder.py ddc fft -d e310 -t E310_RFNOC_sg3 -m 5
> --fill-with-fifos
>
> --Using the following blocks to generate image:
>      * ddc
>      * fft
> Adding CE instantiation file for 'E310_RFNOC_sg3'
> changing temporarily working directory to
> /home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/../../top/e300
> Setting up a 64-bit FPGA build environment for the USRP-E3x0...
> - Vivado: Found (/opt/Xilinx/Vivado/2017.4/bin)
>
> Environment successfully initialized.
> make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq
> PART_ID=xc7z020/clg484/-3 TOP_MODULE=e300 RFNOC=1 E310=1
> EXTRA_DEFS="RFNOC=1 E310=1"
> make[1]: Entering directory '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
> BUILDER: Checking tools...
> * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu)
> * Python 2.7.12
> * Vivado v2017.4 (64-bit)
> ========================================================
> BUILDER: Building IP axi_dma_stream
> ========================================================
> BUILDER: Staging IP in build directory...
> BUILDER: Reserving IP location:
>
> /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
> BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
> BUILDER: Building IP...
> [00:00:00] Executing command: vivado -mode batch -source
> /home/rcetin/rfnoc/src/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log
> axi_dma_stream.log -nojournal
> CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
> /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
> This IP will not be included in the IP Catalog.
> CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
> /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
> This IP will not be included in the IP Catalog.
> CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
> /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/util_ds_buf_v2_1/component.xml.
> This IP will not be included in the IP Catalog.
> CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file
> /opt/Xilinx/Vivado/2017.4/data/rsb/iprepos/intf_aximm_v1_0/component.xml.
> This IP will not be included in the IP Catalog.
> [00:00:13] Current task: Initialization +++ Current Phase: Starting
> [00:00:13] Current task: Initialization +++ Current Phase: Finished
> [00:00:13] Executing Tcl: synth_design -top axi_dma_stream -part
> xc7z020clg484-3 -mode out_of_context
> [00:00:13] Starting Synthesis Command
> [00:00:13] Current task: Synthesis +++ Current Phase: Starting
> ERROR: [filemgmt 56-148]
> @57j-140@/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/xpm_cdc.xml1
> ERROR: [Common 17-53] User Exception: No open design. Please open an
> elaborated, synthesized or implemented design before executing this
> command.
> ERROR: [Common 17-53] User Exception: No open design. Please open an
> elaborated, synthesized or implemented design before executing this
> command.
> ERROR: [Common 17-53] User Exception: No open design. Please open an
> elaborated, synthesized or implemented design before executing this
> command.
> ERROR: [Common 17-53] User Exception: No open design. Please open an
> elaborated, synthesized or implemented design before executing this
> command.
> ERROR: [Common 17-53] User Exception: No open design. Please open an
> elaborated, synthesized or implemented design before executing this
> command.
> ERROR: [Common 17-53] User Exception: No open design. Please open an
> elaborated, synthesized or implemented design before executing this
> command.
> ERROR: [Vivado 12-398] No designs are open
> [00:00:14] Current task: Synthesis +++ Current Phase: Finished
> [00:00:14] Process terminated. Status: Failure
>
> ========================================================
> Warnings:           0
> Critical Warnings:  4
> Errors:             8
>
> BUILDER: Releasing IP location:
>
> /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream
> /home/rcetin/rfnoc/src/fpga/usrp3/top/e300/ip/axi_dma_stream/Makefile.inc:15:
>
> recipe for target
> '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci'
>
> failed
> make[1]: ***
> [/home/rcetin/rfnoc/src/fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_dma_stream/axi_dma_stream.xci]
>
> Error 1
> make[1]: Leaving directory '/home/rcetin/rfnoc/src/fpga/usrp3/top/e300'
> Makefile:70: recipe for target 'E310_RFNOC_sg3' failed
> make: *** [E310_RFNOC_sg3] Error 2
>
> Can you please point me what i did wrong ?
>
> Best Regards.
>
>
> _______________________________________________
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> USRP-users at lists.ettus.com
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>
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