[USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Derek Kozel derek.kozel at ettus.com
Thu Oct 26 11:58:24 EDT 2017

Hello Brais,

Sorry for the long delay. Yes, the B210 has a Spartan 6 which is not
supported by Vivado so the design uses ISE. This, and the smaller size of
the B210's FPGA, is why RFNoC support has not been added to it. All third
generation USRPs support RFNoC and so will all planned future USRPs.

I hope your project is going well and that it is a success.


On Tue, Oct 3, 2017 at 6:22 PM, Brais Ares <bares at gradiant.org> wrote:

> Thank you Derek,
> I was playing around with E300 design, but we actually need to use B2X0
> devices, apparently not supported by RFNoC. Also we need to implement some
> complex decimation and filtering so that FIR block will not be enough.
> I guess, if I'm not mistaken, our only choice is to use Xilinx ISE to
> modify the hdl design.
> Regards,
> Brais.
> 2017-10-03 12:45 GMT+02:00 Derek Kozel <derek.kozel at ettus.com>:
>> Hello Brais,
>> The HDL design does have a top block and is composed of usefully divided
>> sub blocks. It is not however designed using the graphical Vivado workflow,
>> but a source based one. Here is the top block:
>> https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/e300/e310.v
>> Your application however sounds exactly like what the RFNoC architecture
>> was designed for. This architecture, which the E310 implements, allows you
>> to add in a self contained block of functional logic wrapped by an
>> interface supplied by Ettus. I recommend reading this application note and
>> possibly watching this video which introduces the architecture and leads
>> through the creation of a sample RFNoC block.
>> https://kb.ettus.com/Getting_Started_with_RFNoC_Development
>> https://www.youtube.com/watch?v=j-EfyPVpaJ8
>> If you only want to add a filter or two there is already an FIR block
>> which you could either directly make use of or make hopefully minor
>> modifications to meet your needs.
>> https://github.com/EttusResearch/fpga/blob/6996ed662e5ae170e
>> 60ab8cb6de54c362cecf8d2/usrp3/lib/rfnoc/noc_block_fir_filter.v#L141
>> Regards,
>> Derek
>> On Thu, Sep 21, 2017 at 4:48 PM, Brais Ares via USRP-users <
>> usrp-users at lists.ettus.com> wrote:
>>> Hello,
>>> We want to add some blocks to HDL design in E310 device. We followed the
>>> instructions to build Vivado project and it worked okay.
>>> Thing is the built design when opened in Vivado looks this way
>>> <https://www.dropbox.com/s/5w7ari9xlpth4e9/hdl_hierarchy.JPG?dl=0> ...
>>> where design sources hierarchy is kind of complex. I was expecting a top
>>> module or at least not that much sources.
>>> Is there no way to see the design as a block design (like in a typical
>>> Vivado workflow)?
>>> Adding just a few filters to this design implies reverse-engineering
>>> what is going on in most of these source files...
>>> ​Any advice in how to proceed/start is appreciated.
>>> Regards,
>>> Brais.​
>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> --
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> Brais Ares Fernández
> Investigador - Desarrollador | Área de Comunicaciones Avanzadas
> Researcher - Developer | Advanced Communications Department
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