[USRP-users] systemverilog files in rfnoc block

Jade Anderson Jade.Anderson at averna.com
Wed Oct 25 14:06:35 EDT 2017


Hi, 
Below is a question about sytemverilog support from August, that seems unresolved.  
I found this workaround, but why does the scripted flow not support systemverilog design files?
Are there plans to make this change to support designs in sytemverilog?  
  If not, then can you please point me to an example of how to include a synthesized netlist into a build?  I can synthesize my systemverilog module in Vivado for the  X310 with no problems.  
All I need to do is then import it into the x310 build.

Thanks
Jade Anderson


Message: 5
Date: Fri, 25 Aug 2017 19:55:11 +0000
From: Dario Pennisi <dario at iptronix.com>
To: "usrp-users at lists.ettus.com" <usrp-users at lists.ettus.com>
Subject: [USRP-users] systemverilog files in rfnoc block
Message-ID: <1503690911110.91061 at iptronix.com>
Content-Type: text/plain; charset="iso-8859-1"

hi,

i am trying to include a couple of systemverilog files in the list of sources for a custom rfnoc block.

if i do that i can see in the log that all files with .sv extension are ignored and of course their modules are not found. if i launch compilation in gui mode and then add files back it works...

is there any way of avoiding this manual step?

thanks,


Dario Pennisi
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Message: 6
Date: Fri, 25 Aug 2017 20:27:18 +0000
From: Dario Pennisi <dario at iptronix.com>
To: "usrp-users at lists.ettus.com" <usrp-users at lists.ettus.com>
Subject: Re: [USRP-users] systemverilog files in rfnoc block
Message-ID: <1503692838342.55361 at iptronix.com>
Content-Type: text/plain; charset="iso-8859-1"

i think i found the issue...

tcl script file usrp3/tools/scripts/viv_utils.tcl actually contains instructions to add files to project based on their extensions and .sv is not listed so files are skipped.

adding a case for .sv works but it also includes axi_crossbar_intf.sv which seems to be a simulation file and won't compile so i had to exclude that file...

is there any reason why sv files are not included or is that just a lazy way to exclude simulation sources?

unfortunately i need to use some systemverilog constructs and with .v extension those seem not to be accepted...

thanks,


Dario Pennisi




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