[USRP-users] Ettus B210 full design simulation

Petraglio Enrico enrico.petraglio at heig-vd.ch
Mon Oct 16 08:49:26 EDT 2017


Hi,


I'm currently trying to find out a way to simulate the entire b210 architecture.

I've find a "run_sim" command located in the directory :

prefix/rfnoc/src/uhd-fpga/usrp3/top/b200/sim/b2x0/sim_b2x0_1

This command tried to run ISim but all the links looks broken. I've tried to figure out the

best way to fix the links but during the execution I got this error message :


ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Starting static elaboration
ERROR:HDLCompiler:1654 - "../../../../../../top/b200/b200_core.v" Line 184: Instantiating <uart> from unknown module <cvita_uart>
ERROR:HDLCompiler:1654 - "../../../../../../top/b200/b200_core.v" Line 211: Instantiating <reds_block> from unknown module <reds_test_block>
ERROR:HDLCompiler:1654 - "../../../../../../top/b200/b200_core.v" Line 329: Instantiating <radio_0> from unknown module <radio_legacy>
ERROR:HDLCompiler:1654 - "../../../../../../lib/gpif2/gpif2_to_fifo64.v" Line 62: Instantiating <min_read_buff> from unknown module <axi_fifo_legacy>

Since I'm not used with the ISim simulations I'm a bit stuck with this errors at the moment. Can anyone help me out?

Is this the best way to achieve a full B210 simulation or Ettus is providing other methods?

Regards

Enrico







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