[USRP-users] Fast synthesis of SDR's FPGA

Marcus Müller marcus.mueller at ettus.com
Sat Oct 14 06:19:55 EDT 2017


Hi Shoor,

instead of doing the build with our Makefile system, you can[1] also
generate a ISE project (.xise) that you can load in ISE, and build using
ISE:

make PROJECT_ONLY=1 {yourtarget}

In my experience, if anything, this doesn't change the build times
drastically, even for minor modifications to single modules.

Best regards,

Marcus

[1] http://files.ettus.com/manual/md_usrp3_build_instructions.html
On 14.10.2017 02:06, Shoorveer Singh via USRP-users wrote:
> Hi Neel, 
>
> Sorry about the mistake. 
>
> Actually I am trying to implement FFT in the Ettus RX-TX Path.
> Building the code along with the FFT takes much more time as expected. 
> Is there a way to specify  incremental place and route in Xilinx? I am
> hoping that this time can be reduced for small changes in the code, so
> that when rebuilding, I can use the old build files. 
>
>
> --
> Thanks and Regards
> Shoor
>
> From: Neel Pandeya <neel.pandeya at ettus.com
> <mailto:neel.pandeya at ettus.com>>
> Date: Friday, October 13, 2017 at 4:47 PM
> To: Shoorveer Singh <Shoorveer.Singh at privoro.com
> <mailto:Shoorveer.Singh at privoro.com>>
> Cc: usrp-users <usrp-users at lists.ettus.com
> <mailto:usrp-users at lists.ettus.com>>
> Subject: Re: [USRP-users] Fast synthesis of SDR's FPGA
>
> Hello Shoor:
>
> Please keep the conversation on the mailing list.
>
> A build time of 20 minutes for the B200mini FPGA is entirely normal.
> I'm not sure how much you would be able to reduce that. Again, try the
> build on a system with a higher clock speed and at least 8 GB memory.
> Our Xilinx ISE workflow does not have an incremental build process,
> and because Xilinx has ended development and support for ISE (Xilinx
> has deprecated ISE), we do not have any plans to add this capability.
>
> Please let me know if you have any further questions.
>
> --Neel Pandeya
>
>
>
> On 13 October 2017 at 10:43, Shoorveer Singh
> <Shoorveer.Singh at privoro.com <mailto:Shoorveer.Singh at privoro.com>> wrote:
>
>     Hi Neel, 
>
>     I am using USRP B200mini. Even without any modification to the
>     code, it take around 20 minutes to build. 
>
>     Is there a way we can speed up the process so that if I do a small
>     modification to the code, it takes less time? Like incrementally
>     builds?
>
>
>>     Thanks and Regards
>     Shoor
>
>     From: Neel Pandeya <neel.pandeya at ettus.com
>     <mailto:neel.pandeya at ettus.com>>
>     Date: Friday, October 13, 2017 at 10:28 AM
>     To: Shoorveer Singh <Shoorveer.Singh at privoro.com
>     <mailto:Shoorveer.Singh at privoro.com>>
>     Cc: usrp-users <usrp-users at lists.ettus.com
>     <mailto:usrp-users at lists.ettus.com>>
>     Subject: Re: [USRP-users] Fast synthesis of SDR's FPGA
>
>     Hello Shoor:
>
>     How long is your Xilinx ISE build taking? Which USRP device are
>     you using?
>
>     The primary thing would be to use a CPU with a higher clock speed.
>     More memory helps too, as the build process is memory-intensive,
>     but only up to a point. For the B200/B210 FPGA, a system with 8 GB
>     memory should suffice.
>
>     Xilinx ISE won't really take advantage of multiple cores, so using
>     a CPU with lots of cores won't help much.
>
>     --​Neel Pandeya
>
>
>
>
>     ​​
>     On 13 October 2017 at 09:34, Shoorveer Singh via USRP-users
>     <usrp-users at lists.ettus.com <mailto:usrp-users at lists.ettus.com>>
>     wrote:
>
>         Hi, 
>
>         I am trying to modify the Ettus’s FPGA code and build the new
>         code to get the bit file. But it takes a very long time for
>         every build to be done. I am using Xilinx ISE for this work. 
>         Is there any way I can get it to work faster?
>
>
>
>         --
>         Thanks and Regards
>         Shoor
>
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>
>
>
>
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