[USRP-users] rfnoc blocks with multiple inputs/outputs
michael.west at ettus.com
Fri Oct 13 15:32:00 EDT 2017
A block can have any number of inputs and outputs, so 2 inputs and 1 output
is fine. The Split Stream block is an example of an asymmetric block.
The UHD XML description of the Split Stream block can be found here:
The GnuRadio XML description of the Split Stream block can be found here:
Hopefully, those examples will help.
As far as the multiple ports at 200 Msps on a single block, it is a known
issue. The bus clock would need to be raised to the CE clock of 214.286
MHz to allow 2 ports to operate at 200 Msps in one block, but doing that
causes the FPGA build to fail timing. As far as a workaround or trick,
there is a way where you can hack up the core FPGA code and make a single
module with 2 noc_shells connected to separate crossbar ports in the
x300_core code, but that is a bit more involved. If you are daring and
curious, look at the way noc_block_axi_dma_fifo and noc_block_radio_core
blocks are instantiated and connected to the crossbar in x300_core.v
On Wed, Oct 4, 2017 at 11:57 PM, Dario Pennisi via USRP-users <
usrp-users at lists.ettus.com> wrote:
> I am still struggling with a block which should have 2 inputs and 1
> output. Apparently everything is fine with both FPGA and software but the
> second input is not fed with data.
> I could not find any example of an asymmetric block with different number
> of inputs/outputs so I am starting to suspect this is not supported. Can
> anyone tell me if this is the case and I need to add a dummy output?
> Also, when defining block I see that in the xml there is the possibility
> to specify nports parameter so that a single port definition provides more
> than one port. If i set nports=2 for the input I am not sure how to define
> the gnuradio xml descriptor and If I just describe two ports as usual block
> will not initialize properly.
> Finally, I understand that system clock rate on AXI bus is 166 MHz and
> since NOC ports are 64 bits, on X310 a single block should not be able to
> process two input streams at 200 MSPS.
> Even raising AXI bus clock to 200 MHz would fail as but would still not
> provide sufficient overhead for packet headers.
> Is there any suggested trick to handle this situation? Is it eventually
> possible to have a single rfnoc block connect to two AXI ports rather than
> just one?
> Dario Pennisi
> USRP-users mailing list
> USRP-users at lists.ettus.com
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