[USRP-users] Fast synthesis of SDR's FPGA

Neel Pandeya neel.pandeya at ettus.com
Fri Oct 13 13:28:10 EDT 2017

Hello Shoor:

How long is your Xilinx ISE build taking? Which USRP device are you using?

The primary thing would be to use a CPU with a higher clock speed. More
memory helps too, as the build process is memory-intensive, but only up to
a point. For the B200/B210 FPGA, a system with 8 GB memory should suffice.

Xilinx ISE won't really take advantage of multiple cores, so using a CPU
with lots of cores won't help much.

--​Neel Pandeya

On 13 October 2017 at 09:34, Shoorveer Singh via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hi,
> I am trying to modify the Ettus’s FPGA code and build the new code to get
> the bit file. But it takes a very long time for every build to be done. I
> am using Xilinx ISE for this work.
> Is there any way I can get it to work faster?
> --
> Thanks and Regards
> Shoor
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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