[USRP-users] Fast synthesis of SDR's FPGA

Shoorveer Singh Shoorveer.Singh at privoro.com
Fri Oct 13 12:34:59 EDT 2017


I am trying to modify the Ettus’s FPGA code and build the new code to get the bit file. But it takes a very long time for every build to be done. I am using Xilinx ISE for this work.
Is there any way I can get it to work faster?

Thanks and Regards
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