[USRP-users] ADC + DAC Compare of N200 and B200

Derek Kozel derek.kozel at ettus.com
Fri Oct 13 07:51:12 EDT 2017


Hi Kevin,

It is 12 bits each for I and Q, a total of 24 bits per complex sample pair.
It is usual for SDRs to list the resolution of the ADC which is then dual
channel for the I and Q.
https://www.ettus.com/content/files/b200-b210_spec_sheet.pdf

Regards,
Derek

On Fri, Oct 13, 2017 at 12:29 PM, Kevin McGuire <kmcg3413 at gmail.com> wrote:

> Derek or anyone,
>
> Do you know if it's a 12-bits complex on the b200 (6-bit I + 6-bit Q) or a
> 24-bit complex? I always thought it was a 24-bit complex but from what you
> said and what I see in the schematics it is plausible things may not be as
> they seem.
>
> This is ultimately my question but I have a weirdness of going around the
> world to ask it, haha. The exact precision used of the ADC before the FPGA
> for comparison is what I am after - but was also after any details too.
>
> Derek,
>
> Your information is most helpful and id assisting me in getting closer to
> understanding. I sincerely appreciate your help/wisdom and I am most
> thankful for people like you (and others) who voluntarily take their time
> to answer questions. I would know nothing if not for the help of people.
>
> I also feel like a lazy dummy because I just realized I could have looked
> at the schematic and seen how the, what appears to be LVDS enabling pins,
> are configured/connected.
>
> On Oct 13, 2017 5:02 AM, "Derek Kozel" <derek.kozel at ettus.com> wrote:
>
>> Hello Kevin,
>>
>> No, the N200 and B200 do not change the electrical transport modes based
>> on the frequency or bandwidth requested by the application, there is no
>> need. The 12 and 14 digital bits are available at all frequencies. The
>> actual effective number of bits out to the host depends on the ADC
>> performance and the decimation in the FPGA DSP.
>>
>> I have not looked in depth at the design decisions that went into
>> selecting the interfaces but I'm confident that the hardware designers
>> verified the signal integrity.
>>
>> You are correct about the use of the two output DAC. For most
>> daughterboards they are used for I and Q. For the others such as the LFRX
>> and LFTX the two channels can be used either as a complex pair or two real
>> valued channels.
>>
>> Regards,
>> Derek
>>
>>
>>
>> On Fri, Oct 13, 2017 at 5:21 AM, Kevin McGuire via USRP-users <
>> usrp-users at lists.ettus.com> wrote:
>>
>>> This is connected to me investigating power level but the question is
>>> specifically about the number of bits per RX and TX channel between the
>>> N200 and B200. However, I fell into the rabbit hole that Alice went into
>>> and I seem to be stuck for the moment in determining what I am missing.
>>>
>>> I looked at the datasheet for the B200 and the AD9361. The AD9361 is
>>> advertised as using a 12-bit ADC and DAC. However, I see that it can
>>> operate in a 6-bit mode using the inputs as differentials - i suspect that
>>> is useful at ever higher frequencies. I counted 24 data pins.
>>>
>>> Now, the N200 uses this ADS62P42 which is a dual channel ADC. When
>>> looking at the datasheet it has 14 output ports per channel and two
>>> channels. I think this chip can also run in LVDS (differential) or CMOS
>>> (single-ended) modes. I am guessing once again LVDS gives only 7 effective
>>> bits per channel and CMOS gives 14 effective bits per channel.
>>>
>>> It seems that the AD9361 has two data ports where each port uses 12 of
>>> the 24 pins. Each of the data port pins can be an input or output. And,
>>> from what I can read it seems like these data ports can be combined in
>>> various ways, such as:
>>>
>>> 12-bit RX channel + 12-bit TX channel [FDD]
>>>    I = 6-bit and Q = 6-bit (single data rate)
>>> 24-bit RX channel + 24-bit TX channel [TDD]
>>>    I = 12-bit and Q = 12-bit (single data rate)
>>> 12-bit RX1 + 12-bit RX2 + 12-bit TX1 + 12-bit TX2 [FDD]
>>>    I = 6-bit and Q = 6-bit (double data rate)
>>> 12-bit RX1 + 12-bit RX2 + 12-bit TX1 + 12-bit TX2 [TDD]
>>>    We can have only two RX or TX active at the same time. (double data
>>> rate)
>>>
>>> Is this correct? And, which modes are actually used?
>>>
>>> The N200 I believe I have a handle on because it appears more straight
>>> forward. I can see how the RX provides two independent DAC outputs and each
>>> are 14-bit. If I have a handle on it then one should be the in-phase and
>>> the other the quadrature or two separate in-phase depending on the daughter
>>> board.
>>>
>>> Then, I also wonder, does the FPGA/firmware switch between CMOS and LVDS
>>> on either the B200 or the N200 in order to improve quality at higher
>>> frequencies?
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>
>>
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