[USRP-users] ADC + DAC Compare of N200 and B200
kmcg3413 at gmail.com
Fri Oct 13 00:21:12 EDT 2017
This is connected to me investigating power level but the question is
specifically about the number of bits per RX and TX channel between the
N200 and B200. However, I fell into the rabbit hole that Alice went into
and I seem to be stuck for the moment in determining what I am missing.
I looked at the datasheet for the B200 and the AD9361. The AD9361 is
advertised as using a 12-bit ADC and DAC. However, I see that it can
operate in a 6-bit mode using the inputs as differentials - i suspect that
is useful at ever higher frequencies. I counted 24 data pins.
Now, the N200 uses this ADS62P42 which is a dual channel ADC. When looking
at the datasheet it has 14 output ports per channel and two channels. I
think this chip can also run in LVDS (differential) or CMOS (single-ended)
modes. I am guessing once again LVDS gives only 7 effective bits per
channel and CMOS gives 14 effective bits per channel.
It seems that the AD9361 has two data ports where each port uses 12 of the
24 pins. Each of the data port pins can be an input or output. And, from
what I can read it seems like these data ports can be combined in various
ways, such as:
12-bit RX channel + 12-bit TX channel [FDD]
I = 6-bit and Q = 6-bit (single data rate)
24-bit RX channel + 24-bit TX channel [TDD]
I = 12-bit and Q = 12-bit (single data rate)
12-bit RX1 + 12-bit RX2 + 12-bit TX1 + 12-bit TX2 [FDD]
I = 6-bit and Q = 6-bit (double data rate)
12-bit RX1 + 12-bit RX2 + 12-bit TX1 + 12-bit TX2 [TDD]
We can have only two RX or TX active at the same time. (double data rate)
Is this correct? And, which modes are actually used?
The N200 I believe I have a handle on because it appears more straight
forward. I can see how the RX provides two independent DAC outputs and each
are 14-bit. If I have a handle on it then one should be the in-phase and
the other the quadrature or two separate in-phase depending on the daughter
Then, I also wonder, does the FPGA/firmware switch between CMOS and LVDS on
either the B200 or the N200 in order to improve quality at higher
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