[USRP-users] RFNOC complex_multiplier not found

Nicolas Cuervo nicolas.cuervo at ettus.com
Wed Oct 11 07:16:02 EDT 2017


Hello Kau-Uwe,

You have to point your Makefile where the IP is located so that it can
build it for simulation. You can base this on the Makefile for the FIR
filter, for example [1], where the IP specific settings are introduced.

In your specific use case, it should be something like:

#-------------------------------------------------
# IP Specific
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory

IP_DIR = $(BASE_DIR)/x300/ip

# Include makefiles and sources for all IP components
# *after* defining the IP_DIR

include $(LIB_IP_DIR)/complex_multiplier/Makefile.inc
DESIGN_SRCS += $(abspath \
$(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \
)


Regards,
- Nicolas

[1]
> https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/noc_block_fft_tb/Makefile#L14
>


On Wed, Oct 11, 2017 at 9:47 AM, Kai-Uwe Storek via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hey,
>
> if I use an instantiation of rfnoc-devel/usrp3/lib/rfnoc/cmul.v in my
> design, the compilation / elaboration process (make
> noc_block_myblock_tb) fails with:
>
> ERROR: [VRFC 10-2063] Module <complex_multiplier> not found while
> processing module instance <cmult1>
> [/home/labor/gr_prefixes/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cmul.v:13]
> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design
> unit(s) in library work failed.
>
>
> As far as I can see the usrp3/lib/ip/Makefile.inc is correct, but it
> seems that this inc-File is untouched / unused.
>
> Can some point me in the right direction how to make
> "complex_multiplier" discoverable for the "make noc_block_myblock_tb"
> command?
>
> Thanks!
> Kai
>
>
>
> The instantiation snippet of my custom block is:
>
>   generate
>    cmul inst_cmul (
>     .clk(ce_clk), .reset(ce_rst),
>     .a_tdata(in_tdata[0]), .a_tlast(in_tlast[0]),
> .a_tvalid(in_tvalid[0]), .a_tready(in_tready[0]),
>     .b_tdata(in_tdata[1]), .b_tlast(in_tlast[1]),
> .b_tvalid(in_tvalid[1]), .b_tready(in_tready[1]),
>     .o_tdata(out_tdata[0]), .o_tlast(out_tlast[0]),
> .o_tvalid(out_tvalid[0]), .o_tready(out_tready[0]));
>   endgenerate
>
> and without this snippet the testbench runs without any problem.
>
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