[USRP-users] additional Verilog file in OOT RFNoC block

Nicolas Cuervo nicolas.cuervo at ettus.com
Wed Oct 11 06:31:51 EDT 2017


Hello Dixon,

Daniel's suggestion works, but that would mean adding a hard-coded path
into the fpga build system. It does the trick, but it is not recommended.

The OOT module has its own Makefile.srcs that intends to contain all the
HDL code that is required for the module. The procedure is the same: just
add the multTest.v file in the Makefile.srcs located at
your_oot_module/rfnoc/fpga/, as follows (assuming it is located in the same
directory as the noc_block_* file):

$(addprefix SOURCES_PATH, \
> noc_block_your_block.v \
>
*multTest.v \*

) \
>

Don't forget to add the trailing "\".

For simulation in the testbench, the procedure is basically the same. In
the rfnoc/testbenches/noc_block_your_bloc_tb/ directory, there is a
Makefile that would need to have explicit access to that new module in
order to work. You just add the file name below the noc_block:


> SIM_SRCS = \
> $(abspath noc_block_yourblock_tb.sv) \
> $(abspath ../../fpga-src/noc_block_yourblock.v) \
> *$(abspath ../../fpga-src/multTest.v) \*


Please let us know if you are still facing issues with this.

Regards,
- Nicolas

On Wed, Oct 11, 2017 at 8:15 AM, Daniel Rauschen via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hi Jim,
>
> try to add the file multTest.v (with the complete absolute path) in the
> Makefile.srcs located at .../uhd/fpga-src/usrp3/top/x300/.
> At least this worked for me.
>
> Best regards,
>
> Daniel
>
>
>
> On 11.10.2017 03:45, Dixon, James L via USRP-users wrote:
>
> Hi,
>
> I am trying to figure out how to add additional Verilog code in a separate
> .v file and have it build.  For a simple proof-of-concept test, I started
> with the "tutorial" module and the "gain" block, as per the instructions in
> the "Getting Started" document.  I then substituted this code in the
> noc_block_gain.v file:
>
> Instead of:
> wire [31:0] i_mult_gain = i * gain;
> wire [31:0] q_mult_gain = q * gain;
>
> I put this:
> wire [31:0] i_mult_gain;
> wire [31:0] q_mult_gain;
>
> multTest mult1 (
> .i(i),
> .q(q),
> .gain(gain),
> .iout(i_mult_gain),
> .qout(q_mult_gain) );
>
> And then at the end of the noc_block_gain.v file, I added this:
>
> module multTest(i, q, gain, iout, qout);
> input [15:0] i;
> input [15:0] q;
> input [15:0] gain;
> output [31:0] iout;
> output [31:0] qout;
>
> assign iout = i * gain;
> assign qout = q * gain;
> endmodule
>
> This builds fine.  However, I would like to put the multTest module code
> in a separate .v file.  I tried just putting it in a file called multTest.v
> in the same directory as the noc_block_gain.v file, but I get an error that
> the module "multTest" can't be found.  As I mentioned, this is just a
> simple test and my real goal is to put a significant amount of code into
> the additional Verilog file, and to eventually use an additional VHDL file.
>
> Any ideas?  I'm guessing that there may be some additional steps.
>
> Thanks,
>
> Jim
>
>
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