[USRP-users] [RFNoC] How to add chipscope to RFNoC project?
nicolas.cuervo at ettus.com
Thu Oct 5 00:29:20 EDT 2017
Hmmm, do you mind being more specific regarding the part where the synth
fails? Copy/pasting the output you are getting would also be optimal.
Trying my luck here: when the Vivado GUI pops up and you are able to save
the project, be sure that you do NOT check the box that says "Import all
files to the new project" in the "save project" dialog, as doing otherwise
is known for causing synth issues. Also, it would be better if you do
not modify the path where the project is being saved, but only the name. Not
importing the file will preserve paths, and as long as the project is in
the build folder, it should synthesize just fine.
On Wed, Oct 4, 2017 at 10:11 PM, Felipe Augusto Pereira de Figueiredo <
zz4fap at gmail.com> wrote:
> Dear Nicolas,
> Thanks for your prompt reply! I missed that part regarding the
> rfnoc-devel branch. I will try with the devel branch and get back to
> you in case I find some problem.
> Yes, I'm able to stop it, however, when I save and try to synthesize
> the project again vivado complains that some files/libs are missing
> and I have not changed anything, I'm just trying to generate the image
> so that I know everything works without any modification from my side.
> Thanks and Kind Regards,
> Felipe Augusto
> On Wed, Oct 4, 2017 at 7:15 PM, Nicolas Cuervo <nicolas.cuervo at ettus.com>
> > Felipe,
> > the uhd_image_builder.py  is located in the usual location described
> > that guide :
> > path_to_fpga_repo/usrp3/tools/scripts/
> > Be sure to be pointing to the rfnoc-devel branch.
> > I don't understand what you mean with "when I run make GUI=1 X310_HG I'm
> > able to stop the synthesis". You should be able to do so when the
> > GUI pops up. This part of the process is the same when using the command
> > described or the uhd_image_builder.
> > Regards,
> > - Nicolas
> > 
> > https://github.com/EttusResearch/fpga/blob/rfnoc-
> > 
> > https://kb.ettus.com/Debugging_FPGA_images#Save_the_project_and_finish_
> > On Wed, Oct 4, 2017 at 6:58 PM, Felipe Augusto Pereira de Figueiredo via
> > USRP-users <usrp-users at lists.ettus.com> wrote:
> >> Dear All,
> >> One question, I'm trying to add a chipscope to my project but I'm not
> >> finding uhd_image_builder.py script and when I run make GUI=1 X310_HG
> >> I'm not able to stop the synthesis and after the FPGA image is
> >> generated I save the project but I'm not able to use the saved project
> >> for adding my chipscope.
> >> I think the information here:
> >> https://kb.ettus.com/Debugging_FPGA_images is outdated.
> >> Have you removed the uhd_image_builder.py script? If so, is there a
> >> replacement for that script?
> >> Any hint will be very helpful! Thanks!
> >> Thanks and Kind Regards,
> >> Felipe Augusto
> >> _______________________________________________
> >> USRP-users mailing list
> >> USRP-users at lists.ettus.com
> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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