[USRP-users] issue with RFNoC signal generator block on X310 (TLDR)

Dario Pennisi dario at iptronix.com
Tue Nov 28 10:59:21 EST 2017


Hi,
A short question for which there is a larger underlying issue: if I connect a RX RFNoC Radio block to a TX RFNoC radio block, regardless of the presence of FIFOs in the middle nothing gets transmitted.
The only way it works seems to be by passing through the host by inserting two fifos and something like a mult const block on the host side so that data goes back and forth to/from the host.
Is there any reason this is happening?

Now the TL;DR part... for which I did this test:

I am developing a complex block with 3 inputs and 3 outputs. It is basically a transceiver block in which channels are configured this way:

In 0        packet data in
In 1        RF data in from RX0
In 2        RF data in from RX1
Out 0     Packet data out
Out 1     RF Data out to TX0
Out 2     RF Data out to TX1

Basically I have a streaming input from the host that contains data packets that are modulated and output on one of the two RF ports that will be connected to radios.
On the opposite side I have two radio blocks connected to input ports 1 and 2 and which are demodulated and output as packets on output port 0
Since rfnoc works at 200 MSPS by default and since bus does not have enough bandwidth I reduced system clock frequency to 120 MHz using device3 block in gnuradio. This way overall bandwidth (166 MHx x 64 bit) is still less than what I am handling (2x 120MSPS @ 32 bit + 1x very low bandwidth channel).
Rx side works perfectly while TX side seems to have an issue. First of all I want to transmit in bursts at given timestamps so my tuser packets would contain valid timestamp for first packet of the burst and will contain end of burst on the last packet. Unfortunately I have not gone as far as this since when I start transmitting I see that after a few packets my block receives a low ready which halts it after some packets (around 6).
Checking radio block I can see it receives some packets (less than the ones transmitted) and then it sets ready low after it sees tvalid low and subsequently status is set to underrun.
After this everything is locked up and I have to reprogram FPGA in order to restart it.
Suspecting that packets where too small I increased their size to the same of the signal generator block sample but with no results.
Now the question is what could be going wrong? It should not be an issue with bandwidth and I don't see why packets seem to be lost somewhere although I see that after a short while things freeze up and packets don't make it to the radio.
This is the reason why I tested the radio loopback and now I am suspecting there is some issue with UHD drivers that may not enable correctly all the routing paths if host is not in the loop for the tx part.

Thank you,

Dario Pennisi

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