[USRP-users] Design Checkpoints (dcp-files) in RFNoC-OOT-modules

Anselm Karl anselmkarl.inbox at googlemail.com
Tue Nov 21 09:25:15 EST 2017


for quite a time (with breaks) am working on RFNoC Blocks based on Xilinx
System Generator. The only feasable way to integrate the System Generator
model into a RFNoC block, I found, was making a design checkpoint
(.dcp-file) out of it and importing it into Vivado. Integrating all the
verilog sources and ip cores is very messy.

Adding the .dcp to the make source files never worked for me. I used a the
GUI_MODE option to get a Vivado Project i could add the .dcp to.

The make environment doesen´t accept .dcp, as they are not listet in
"viv_utils.tcl" in the "section initialize_project". With a simple
modifcation (  {.dat} => {.dat .dcp}  ) it seems to work.

I see no Option to integrate a .dcp into oot module without this "hack".
Maybe you should simply incoporate this "hack" into the rfnoc-devel branch.
Alternatively you could add some socket or placeholder in the tcl-scripts
for oot-module tcl code.

Of maybe there is an Option, I don't see. I am not fit with make and tcl.


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