[USRP-users] USRP2 schematic vs. FPGA source discrepancy
michal.a.wrobel at gmail.com
Thu Nov 9 05:23:50 EST 2017
BTW. I found that this question has been already asked a long time ago:
but it didn't get any answers back then.
Thanks Ian for the full explanation.
2017-11-09 10:15 GMT+01:00 Ian Buckley <ianb at ionconcepts.com>:
> There’s a bit of history there. PHY_CLK was indeed originally connected to
> the FPGA.
> It wasn’t needed and so the S1 switch was added to that pin instead.
> That switch was never used and so the original signal name persists in the
> Verilog even though it connects to nothing.
> On Nov 5, 2017, at 5:44 AM, Michał Wróbel via USRP-users <
> usrp-users at lists.ettus.com> wrote:
> Hi Robin,
> Thank you for the information.
> I experimented a bit and it turned out that the V15 pin is indeed
> connected to SW1, so the schematic was more informative here. The USRP2
> FPGA source code has the pin declared, but it is not used at all
> Best regards,
> 2017-11-04 17:53 GMT+01:00 Robin Coxe <robin.coxe at ettus.com>:
>> Hi Michal. The USRP2 is a discontinued product that was introduced
>> before Ettus Research was integrated into the National Instruments
>> manufacturing infrastructure. Unfortunately, the only schematics and
>> FPGA pin constraints files that we have on hand are the ones that you have
>> already located. All of the people who were involved in developing the
>> USRP2 no longer work at Ettus Research.
>> The Xilinx XC3S2000 FPGA used on the USRP2 is the FG456 package.
>> Detailed information about the pinout can be found starting at p. 175 of
>> the Xilinx datasheet: https://www.xilinx.com/support/documentation/
>> You could try powering on the board and probing pin V15 with an
>> oscilloscope to see if you observe either a clock signal or a pulse when
>> you press SW1. If I had to guess, the FPGA constraints file is most likely
>> more up to date than the schematic.
>> If you would prefer to develop on a USRP that is still a released and
>> actively supported, you might consider the USRP N200 or N210.
>> On Sat, Nov 4, 2017 at 5:37 AM, Michał Wróbel via USRP-users <
>> usrp-users at lists.ettus.com> wrote:
>>> Dear usrp-users,
>>> Maybe you've got the answer to my question below.
>>> ---------- Forwarded message ----------
>>> From: Michał Wróbel <michal.a.wrobel at gmail.com>
>>> Date: 2017-10-28 19:32 GMT+02:00
>>> Subject: USRP2 schematic vs. FPGA source discrepancy
>>> To: support at ettus.com
>>> Dear Ettus Research support team,
>>> I am considering customizing USRP2 FPGA contents, however there seems to
>>> be a discrepancy between USRP2 schematics
>>> <https://files.ettus.com/schematics/usrp2/usrp2.pdf> and FPGA
>>> constraints file
>>> On the schematics the pin V15 is connected to S1 switch, while the
>>> constraints file attaches this pin to PHY_CLK signal. Is it possible that
>>> the schematics and the constraints file are for different revisions of
>>> USRP2 hardware?
>>> Judging from the filename I presume the FPGA constraints file is for
>>> "revision 3". Which hardware revision do the schematics describe? Where can
>>> I find schematics and FPGA constraints file for "USRP2 Rev 4.0", which I
>>> Thank you in advance,
>>> Michał Wróbel
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
> USRP-users mailing list
> USRP-users at lists.ettus.com
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the USRP-users