[USRP-users] Phase Alignment of Multiple X310s

Marcus D. Leech mleech at ripnet.com
Tue Nov 7 13:15:33 EST 2017


On 11/07/2017 12:32 PM, Rob Kossler wrote:
> Yes, y0 and  y1 on first motherboard, y2 and y3 on second 
> motherboard.  Unfortunately, I don't know of any options to improve it.
>
> Rob
This is likely, as you point out, due to mutual phase-noise of the 
reference PLLs between X310s.   I'll let the Ettus hardware people comment
   on whether any improvement is possible.

It's a bit surprising that the mutual phase-noise on same-motherboard 
UBX is as good as it is, since two PLL synthesizers will have some remaining
   mutual phase-noise even when locked to the same, high-quality, 
reference. The VCOs are operating independently--they won't be "zigging"
   and "zagging" at the same time.

>
> On Tue, Nov 7, 2017 at 11:28 AM, ROBIN TORTORA <tilla at comcast.net 
> <mailto:tilla at comcast.net>> wrote:
>
>     On the UBX results, Y0 -> Y1, I assume that is in the same
>     motherboard?
>
>
>     Y2 and Y3 on a different motherboard (delta seems to be much
>     larger, but very very similar across Y2 and Y3 relative to Y0)?
>
>
>     So if I wanted to improve on the "error" on channels 3 and 4 or
>     add more channels, are there any options?
>
>
>     Lets assume I have done the easy things like match cable lengths
>     and use splitters with low phase balance etc. :)
>
>>     On November 6, 2017 at 6:33 PM Rob Kossler via USRP-users
>>     <usrp-users at lists.ettus.com <mailto:usrp-users at lists.ettus.com>>
>>     wrote:
>>
>>     Sarah,
>>     I just happen to be in the middle of an evaluation presently of
>>     the channel-to-channel phase coherence among various 4 chan
>>     receivers, among them an X310/UBX (pair) and X310/TwinRx.  For
>>     this test, I inject a CW tone (-48 dBm) into a 1:4 power divider
>>     which then feeds the four receiver channels. I then compute the
>>     cross correlation (in 1 msec blocks, zero lag) between each of
>>     channels 2-4 and channel 1 (arbitrarily selected as the reference
>>     channel).  The following figure shows the channel-to-channel
>>     phase variation over a 2 sec window.  The left plots are for the
>>     four channel X310/TwinRx.  The right plots are for the pair of 
>>     X310/UBX (appropriately synced).   The 3 plots for each device
>>     show channels 2-4 in comparison to channel 1.  Note that the
>>     TwinRx results show much smaller variation (as expected since
>>     there is a shared LO).  Also note that for UBX results, the
>>     variation is much smaller for the two channels that are housed in
>>     the same X310 (top right plot).  I suspect that the much larger
>>     variations shown for the 3rd and 4th channels (relative to
>>     channel 1) are related to a 10 MHz PLL circuit in each X310. 
>>     Bottom line is that I see at least +/- 1 degree "wobble" in the
>>     channel-to-channel phase over time. You'll need to determine if
>>     this is acceptable for your application.
>>
>>     Rob
>>
>>
>>     Inline image 1
>>
>>
>>     On Mon, Nov 6, 2017 at 5:11 PM, Marcus D. Leech via USRP-users
>>     <usrp-users at lists.ettus.com <mailto:usrp-users at lists.ettus.com>>
>>     wrote:
>>
>>         On 11/06/2017 04:57 PM, Sarah Tran via USRP-users wrote:
>>>
>>>         Hi everyone!
>>>
>>>         I was wondering if anyone knew if it was possible to phase
>>>         align more than 2 X310s (with UBX daughterboard) to form a
>>>         coherent array? I know that 2x2 MIMO is possible using a
>>>         single X310, but I want to be able to sync 4 of them. I
>>>         thought I read somewhere that it was dependent on the
>>>         daughterboard, but I can’t find that thread anywhere.
>>>
>>>         Thanks for all the help!
>>>
>>         Yes, use an external 10MHz reference and 1PPS source, like
>>         the Octoclock, or Octoclock-G, or similar.
>>
>>         Also, see this App note:
>>
>>         https://kb.ettus.com/Synchronization_and_MIMO_Capability_with_USRP_Devices
>>         <https://kb.ettus.com/Synchronization_and_MIMO_Capability_with_USRP_Devices>
>>
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