[USRP-users] process improvement
Jade.Anderson at averna.com
Mon Nov 6 12:19:08 EST 2017
One thing that seems like an easy improvement to the USRP fpga build process would be to check that all the source files are present prior to launching a 2 hour process.
If you are missing an RFNOC OOT module, then it isn't until after the build-ip step is finished that you find out that your module is not there.
ERROR: [Synth 8-439] module 'noc_block_some_name' not found [/home/<somepathname>/fpga/usrp3/top/x300/rfnoc_ce_auto_inst_x310.v:22]
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