[USRP-users] timout issue on RFNoC output
jonathon.pendlum at ettus.com
Fri Jul 21 14:52:48 EDT 2017
Here is what should happen on the axi stream bus to the crossbar. You
should first see the header on o_tdata with o_tvalid asserted. After a few
clock cycles, depending on how long arbitration takes, you should see
o_tready assert. Are you seeing that sequence?
On Fri, Jul 21, 2017 at 11:48 AM, Jason Matusiak via USRP-users <
usrp-users at lists.ettus.com> wrote:
> I am still struggling with my "output only" RFNoC block and can't seem to
> figure out what silly thing I am doing wrong.
> I am generating data by reading from a ROM and can see it happening by
> monitoring the o_tdata (etc) lines coming from my lower module. If I look
> in my noc_block_dataGenerator.v file, I can see that s_axis_data_tdata
> (etc) looks reasonable going into the axi_wrapper from my lower module.
> Coming out of the axi_wrapper, str_src_tdata (etc) also looks reasonable
> going into noc_shell.
> Looking in noc_shell, I can track the data up to the point where o_tdata_b
> (etc) looks good. But when I look at o_tdata back in
> noc_block_dataGenerator, I don't see any data.
> That to me narrows it down to the axi_fifo_2clk out_fifo module, but I
> don't see why that would be an issue (it is a pretty straightforward block).
> Is there something in my rambling above that points to something silly
> I've done? I am pretty sure this has something to do with the fact that I
> don't have an input to my block (since I have no issues with blocks that
> have an input and an output), but I can't figure out what...
> USRP-users mailing list
> USRP-users at lists.ettus.com
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