[USRP-users] B2XXmini PPS reference jumping around

Neel Pandeya neel.pandeya at ettus.com
Wed Jul 19 22:32:46 EDT 2017


Hello Sean:

You are correct that the control voltage is changed/updated every 1 second.
Unfortunately, there is no simple register setting in the FPGA for the gain
value applied to the detected error. The only way to change the gain value
is to build an FPGA image with custom changes. For a PPS input, the gain is
applied on this line [1]. Currently, there is a gain value of 15 applied to
the error. You can reduce the gain as much as required by your application
by modifying the Verilog code and building a custom FPGA image based on
that modification with Xilinx ISE 14.7. Changing the update rate of the
control voltage is a much more invasive change that would not be quick or
easy to implement.

By the way, the 5ppm specification for the TCXO refers to the adjustment
range of the VCTCXO. The datasheet for the TCXO is on the KB page [2].

[1]
https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/b2xxmini/b205_ref_pll.v#L237

[2]
https://kb.ettus.com/B200/B210/B200mini/B205mini#Key_Component_Datasheets

Please let me know if you have any further questions.

--​Neel Pandeya




On 21 June 2017 at 11:43, Sean Nowlan via USRP-users <
usrp-users at lists.ettus.com> wrote:

> To Whom It May Concern:
>
> I'm using a B200mini (we also have some B205minis which I believe behave
> exactly the same). I'm working on a narrowband application that requires a
> precise clock due to susceptibility to carrier frequency offset. So far
> we've been using a 1PPS as a reference, which gives good accuracy, better
> than 100ppb. However, I've noticed that the frequency reference jumps in
> discrete steps at 1 second intervals, leading me to believe that the
> control voltage to the VCTCXO is updated at the 1PPS edge, and the loop
> filter bandwidth in the digital PLL implementation [1] may be too wide. Do
> you have any recommendations for greatly reducing the discrete jumps, e.g.,
> by greatly narrowing the bandwidth of the loop filter? In our application
> it won't be a problem to let the PLL converge over a long period
> (hours/days).
>
> Also for clarification, past emails on the list about the TCXO stability
> refer to its accuracy (over temperature, I'm assuming) as +/- 0.5ppm.
> However the code [1] states that the TCXO is 5ppm. What are these numbers
> referring to, and which one is correct?
>
> Thanks,
> Sean Nowlan
>
> [1] https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b2xxmini/
> b205_ref_pll.v
>
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20170719/0b901c6d/attachment-0002.html>


More information about the USRP-users mailing list