[USRP-users] E310_sg3 FPGA Verilog code heirarchy

Martin Braun martin.braun at ettus.com
Tue Jul 18 19:07:09 EDT 2017


On 07/18/2017 02:41 PM, Estrada Lupianez, Jenniffer Marie via USRP-users
wrote:
> Can anyone point to any documentation or give some insight on how the
> E310 FPGA Verilog code design is laid out? I am not familiar with
> Verilog, and just extrapolating from what I understand from VHDL. What
> is the top level module? The e310.v file? What is the structure? I
> cannot find any documentation on the FPGA code other than the build
> instructions found here:
> 
> https://files.ettus.com/manual/md_usrp3_build_instructions.html and the
> comments in the verilog code itself. Is there anything else in terms of
> documentation?

Hi Jenn,

that's pretty much it. If you know VHDL, you'll have very little trouble
understanding Verilog though.

e310.v is the top-level. E310-specific modules are also in
usrp3/top/e310. We also pull in a lot of modules from usrp3/lib/*.

Cheers,
Martin




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