[USRP-users] E310_sg3 FPGA Verilog code heirarchy
Estrada Lupianez, Jenniffer Marie
jme at lanl.gov
Tue Jul 18 17:41:50 EDT 2017
Can anyone point to any documentation or give some insight on how the E310 FPGA Verilog code design is laid out? I am not familiar with Verilog, and just extrapolating from what I understand from VHDL. What is the top level module? The e310.v file? What is the structure? I cannot find any documentation on the FPGA code other than the build instructions found here:
https://files.ettus.com/manual/md_usrp3_build_instructions.html and the comments in the verilog code itself. Is there anything else in terms of documentation?
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