[USRP-users] E310 GPIO
ejkreinar at gmail.com
Sat Jul 15 08:39:11 EDT 2017
This particular problem sounds reasonable straightforward with a few fpga
edits. I have successfully commandeered a few gpios in the E310 before for
scoping a couple clock signals.
One possible suggestion for a quick fix: when you set a master clock rate,
then the radio_clk wire in the fpga will run at that frequency. So at 1
MHz, radio_clk would be high for 0.5 us, low for 0.5 us. This is by
definition synchronized with the digital sampling. I'd buffer it with a
higher rate signal (bus_clk, for example, which runs at 50 MHz), then you
could pretty easily route it out one of the gpios.
Hope that helps,
On Jul 14, 2017 4:58 PM, "Marcus D. Leech via USRP-users" <
usrp-users at lists.ettus.com> wrote:
On 07/11/2017 11:56 AM, Will Thompson via USRP-users wrote:
So I’m thinking of starting a project with the E310 that requires high
accuracy control of a switch.
Basically I need to receive a single RF sample (@1MHz) (1us), then send a
signal via the GPIO on a second sample (2us), and then receive a signal
again on the third sample (3us) and alternate between these functions for a
period of time.
I was wondering if anyone has experience with controlling the GPIOs on the
E310, and knows how accurate you can synchronise the signal outputs with RF
received samples? i.e. Can I synchronise the GPIO signalling and the
received RF sampling down to micro seconds?
Also, if anyone has any good resource links for the E310 and GPIO could you
pass them on please?
The GPIO interface is normally accessed using UHD host-side API elements,
which operate asynchronously to the sample stream, so there's no way
to guarantee really-tight timing.
You'd likely need to dive into FPGA coding to achieve this type of
Has a little bit of information, but deep answers to your query can be
found in the FPGA source code.
William Thompson Ph.D.
Senior Research Engineer
Toshiba Research Europe Limited
32 Queen Square, Bristol, BS1 4ND, UK
Tel: +44 (0) 117 906 0734
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