[USRP-users] RFNoC Data Scaling and Representation

Marcus Müller marcus.mueller at ettus.com
Mon Jul 10 15:36:49 EDT 2017


Dear Siraj,

only regarding the dBm issue:

The USRP is not calibrated. There's no dBm standard anywhere in the
system, only digital power (which is really just the magnitude square of
the complex samples), which is /proportional/ to the physical power, but
not the same. The proportionality factor depends on center frequency,
gain, inter-device differences, temperature... and you will need to
calibrate yourself if you want to convert digital power to Watt or dBm.

> I understand that data in FPGA are represented in 16-bit fixed-point.
> I have another set of questions that I would love to have them
> answered. But frankly speaking, above two points are my main concern.
>
>  
>
> 1- I understand that the range of numbers I can represent is -1 ~
> 0.99997 correct?
>
You can do that. It's an /interpretation/ of the bits, that's just as
valid as understanding them as -2^15 ~ 2^15-1.
>
> 2- When numbers out of this range are passed, overflow happens, right?
> I guess everything is saturated at 0.9997 and -1?
>
No, not in general. That depends on what operation you're looking at. In
any case, the ADC will NOT produce numbers outside the range.
>
> 3- Data from host to FPGA are always considered float and mapped to
> 16-bit fixed-point?
>
That's done on the host computer, and yes, by default, UHD does that.
>
> Conversely, data from FPGA to host are always mapped back to float?
>
If you want to, you can ask UHD to give you float, but you can also ask
it to give you signed int16.
>
> Can I interpret them differently without conversion?
>
That'd be item32s – a tuple of 16bit integers
> 4- What about user registers? I assume they are passed as is and I
> have to take care of converting them to fixed-point in my CE if ever
> used with data buses. Correct?
Correct.

Best regards,

Marcus


On 10.07.2017 20:27, Muhammad, Siraj via USRP-users wrote:
>
> Hello All,
>
>  
>
> I have posted several questions previously trying to understand
> something but it only got me more confused.
>
> So let me put this straight.
>
> 1- I am trying to read the output of the Log Power RFNoC block **in dBm**.
>
> 2- I want to write a CE that compares these samples against a
> threshold entered as a user setting register **in dBm**.
>
>  
>
> I understand that data in FPGA are represented in 16-bit fixed-point.
> I have another set of questions that I would love to have them
> answered. But frankly speaking, above two points are my main concern.
>
>  
>
> 1- I understand that the range of numbers I can represent is -1 ~
> 0.99997 correct?
>
> 2- When numbers out of this range are passed, overflow happens, right?
> I guess everything is saturated at 0.9997 and -1?
>
> 3- Data from host to FPGA are always considered float and mapped to
> 16-bit fixed-point? Conversely, data from FPGA to host are always
> mapped back to float? Can I interpret them differently without conversion?
>
> 4- What about user registers? I assume they are passed as is and I
> have to take care of converting them to fixed-point in my CE if ever
> used with data buses. Correct?
>
>  
>
> I appreciate your support.
>
>  
>
> Thanks,
>
> Siraj
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20170710/dc2fc743/attachment-0002.html>


More information about the USRP-users mailing list