[USRP-users] [N210] AD9510 Configuration Issues

Martin Braun martin.braun at ettus.com
Wed Jul 5 20:57:11 EDT 2017


Florian,

you can fetch all the register reads from the appropriate files:

https://github.com/EttusResearch/uhd/blob/maint/host/lib/usrp/usrp2/clock_ctrl.cpp

would be a good place to start.

Cheers,
Martin

On 05/29/2017 06:13 AM, Galler Florian via USRP-users wrote:
> Hello all,
> 
>  
> 
> I am running the N210 with a custom developed Fpga image, because I
> needed the full sampling rate of the ADC and DAC. However, I have
> problems with the configuration of the AD9510. With my settings, it
> seems that the PLL of the AD9510 needs 500ms to lock to the 10 MHz
> internal reference (5MHz PDF and 3mA CP current as stated in the N2XX
> schematics). Sometime it takes even longer. Could you please provide the
> register setting used with the UHD driver or other working register
> settings?
> 
>  
> 
> I want to connect two USRPs with a MIMO cable and synchronize the
> sampling clocks. Could you please give me tips how to configure the
> AD9510s.
> 
> I now have configured the master to provide a 100 MHz ref signal over
> the MIMO cable. The clock switch (U18) of the slave is configured to the
> Mimo cable input (clk_exp_in). The PLL’s phase detector runs at 5 MHz
> and all other settings like in the single unit case.
> 
> To check the synchronization I have connected a scope to the testclk
> output of master and slave. I triggered on the clock of the master and
> activated persistence. At first, it seems that the two clocks are
> synchronized (see picture 1). However, after some time the phase lock is
> lost for short periods of time, which can be seen in the persistent
> trace (see picture 2).
> 
>  
> 
> I also have tried to simulate/calculate the loop filter by ADIsim CLK
> but I didn’t managed to simulate the values of the schematic by entering
> the design parameters (3kHz BW, 45 deg Phase margin with 5 MHz compare
> freq and 3mA CP current).
> 
>  
> 
> Looking forward to your reply
> 
>  
> 
> Florian
> 
>  
> 
> 
> 
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> 





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