[USRP-users] Sampling rates slower than 200 MSps on X310
martin.braun at ettus.com
Wed Jul 5 17:35:52 EDT 2017
On 07/05/2017 01:50 PM, Leandro Echevarría via USRP-users wrote:
> Hello all again,
> I've got a quick question: how does the FPGA core handle sample rates
> slower than the max rate on the X310? I haven't found any strobe signal
> that could indicate when there is valid data coming from the ADC and
> into the x300_core.v: does this mean that it always samples at 200 MSps
> and then downsamples using the DDC block whenever necessary? This comes
> from understanding the radio_clk always stays at 200 MHz.
Exactly right. We can tune and decimate (in integer factors) on the FPGA.
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